谁能告诉我？？？？？？？？？？？？？？？？？？？？？？、
这是我做的电梯程序的一部分，出现了几个问题module dianti(clk,reset,Topen,Tclose,open,close,Oup,Odown,topen,tclose,up,down,anniu2,floor,shu,recode0);
input clk,reset,Topen,Tclose,open,close;//Topen,Tclose:dianti men zhuangtai;open,close:dianti nei anniu
input up,down;//up~up:1~8 ceng shangcheng anniu;down~down:1~8 ceng xiajiang anniu
output Oup,Odown,topen,tclose;
output recode0;
input anniu2,floor,shu;
wire Topen,Tclose,open,close,reset,clk;
wire floor,up,down,anniu1,anniu2,shu;
wire tclose1,topen1,Oup,Odown,topen,tclose;
reg dt,dt1,dt2;
wire topen2,tclose2;
wire recode0, recode1,recode2,recode3,recode4,recode5,recode6,recode7;
wire recode01, recode11,recode21,recode31,recode41,recode51,recode61,recode71;
wire recode02, recode12,recode22,recode32,recode42,recode52,recode62,recode72;
integer i,j,k;
men a1(reset,clk,close,open,topen2,tclose2,Oup,Odown);
anniu b1(reset,clk,anniu2,recode02, recode12,recode22,recode32,recode42,recode52,recode62,recode72);
zhongzhi c1(reset,clk,Oup,Odown,floor,recode01, recode11,recode21,recode31,recode41,recode51,recode61,recode71,tclose1,topen1);
shangxia d1(reset,clk,Oup,Odown,floor,recode0);
zhihuan e1(reset,clk,up,down,anniu1);
assign tclose=tclose2 || tclose1;
assign topen=topen2 || topen1;
endmodule
module anniu(reset,clk,anniu,recode0, recode1,recode2,recode3,recode4,recode5,recode6,recode7);
input reset,clk;
input anniu;
inout recode0, recode1,recode2,recode3,recode4,recode5,recode6,recode7;
wire reset,clk;
wire anniu;
wire recode0, recode1,recode2,recode3,recode4,recode5,recode6,recode7;
reg recode;
integer i,a,b,c;
always @(reset or clk)
begin
a=0;b=0;
if(reset)
for(i=0;i<=7;i=i+1)
recode<=0;
elsebegin
if(anniu) begin
for(i=0;i<=7;i=i+1)
if(recode==1)
b=1;
if(b==0) begin
recode=1;a=a+1; end
end
else if(anniu) begin
for(i=0;i<=7;i=i+1)
if(recode==2)
b=1;
if(b==0) begin
recode=2;a=a+1; end
end
else if(anniu) begin
for(i=0;i<=7;i=i+1)
if(recode==3)
b=1;
if(b==0) begin
recode=3;a=a+1; end
end
else if(anniu) begin
for(i=0;i<=7;i=i+1)
if(recode==4)
b=1;
if(b==0) begin
recode=4;a=a+1; end
end
else if(anniu) begin
for(i=0;i<=7;i=i+1)
if(recode==5)
b=1;
if(b==0) begin
recode=5;a=a+1; end
end
else if(anniu) begin
for(i=0;i<=7;i=i+1)
if(recode==6)
b=1;
if(b==0) begin
recode=6;a=a+1; end
end
else if(anniu) begin
for(i=0;i<=7;i=i+1)
if(recode==7)
b=1;
if(b==0) begin
recode=7;a=a+1; end
end
else if(anniu) begin
for(i=0;i<=7;i=i+1)
if(recode==8)
b=1;
if(b==0) begin
recode=8;a=a+1; end
end
else begin
recode=0;a=a;
end
if(a==7)
a=0;
end
end
assignrecode0=recode;
assign recode1=recode;
assign recode2=recode;
assign recode3=recode;
assign recode4=recode;
assign recode5=recode;
assign recode6=recode;
assign recode7=recode;
endmodule
module zhongzhi(reset,clk,Oup,Odown,floor,recode0, recode1,recode2,recode3,recode4,recode5,recode6,recode7,tclose,topen);
input reset,clk,Oup,Odown;
input floor;
output tclose,topen;
inout recode0, recode1,recode2,recode3,recode4,recode5,recode6,recode7;
wire recode0, recode1,recode2,recode3,recode4,recode5,recode6,recode7;
reg recode;
reg topen,tclose;
integer i,a,b;
always @(reset or clk)
begin
a=0;b=0;
recode=recode0;
recode=recode1;
recode=recode2;
recode=recode3;
recode=recode4;
recode=recode5;
recode=recode6;
recode=recode7;
if(reset) begin
recode=0;
recode=0;
recode=0;
recode=0;
recode=0;
recode=0;
recode=0;
recode=0;end
else begin
if(floor==recode)
if(!Oup)
if(!Odown)
begin
topen=1;
tclose=0;
for(i=0;i<=6;i=i+1)
recode=recode;
end
end
end
assignrecode0=recode;
assign recode1=recode;
assign recode2=recode;
assign recode3=recode;
assign recode4=recode;
assign recode5=recode;
assign recode6=recode;
assign recode7=recode;
endmodule
module men(reset,clk,close,open,topen,tclose,Oup,Odown);
input reset,clk,close,open,Oup,Odown;
output tclose,topen;
reg tclose,topen;
wire reset,clk,close,open,Oup,Odown;
always @(reset orclk)
begin
if(reset)begin
tclose=1;
topen=0;
end
else begin
if((Oup==1)||(Odown==1)) begin
tclose=1;
topen=0;
end
else if((close==1)&&(open==0)) begin
tclose=1;
topen=0;
end
else if((close==0)&&(open==1)) begin
tclose=0;
topen=1;
end
else
begin
tclose=0;
topen=1;
end
end
end
endmodule
module shangxia(reset,clk,Oup,Odown,floor,shu);//panding shangsheng haishi xiajiang
input reset,clk;
input floor,shu;
output Oup,Odown;
reg Oup,Odown;
wire floor,shu;
integer a,b,i;
always @(reset or clk)
begin
a=0;b=0;
for(i=0;i<=7;i=i+1)
begin
if(floor)
a=a+2^i;
if(shu)
b=b+2^i;
end
if(reset)begin
Oup=0;
Odown=0;end
else
begin
if(b<a)
begin
Oup=0;
Odown=1;
end
else if(b>a)begin
Oup=1;
Odown=0;end
else begin
Oup=0;
Odown=0;end
end
end
endmodule
module zhihuan(reset,clk,up,down,anniu1);
input reset,clk;
input up,down;
output anniu1;
reg anniu1;
integer i;
always @(reset or clk)
begin
if(reset)
anniu1=0;
else
for(i=0;i<=7;i=i+1)
if(up)
anniu1=i;
if(down)
anniu1=i;
end
endmodule
1.仿真时inout的端口不连线。
2.如果要anniu能分时间段轮流被anniu1和anniu2赋值该如何做？ 电梯程序例子很多 没有把INOUT信号区分开来，应该分成input 和output,然后处理就简单多了
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