请教 关于边缘脉冲检测的问题
为什么led_d1, led_d2,led_d3 是在led_ctrl,led_ctrl,led_ctrl 下降沿被触发，为什么不是上升沿被触发。
下面是 程序，这是一个利用边缘脉冲检测进行 按键的操作。谢谢。
module lesson9( clk,
rst_n,
sw1_n,sw2_n,sw3_n,
led_d1,led_d2,led_d3,
led_ctrl
);
input clk;
input rst_n;
input sw1_n,sw2_n,sw3_n;
output led_d1,led_d2,led_d3;
output led_ctrl;
reg key_rst;
always @(posedge clk or negedge rst_n)
if(!rst_n)
key_rst<=3'b111;
else
key_rst<={sw3_n,sw2_n,sw1_n};
reg key_rst_r;
always @(posedge clk or negedge rst_n)
if(!rst_n)
key_rst_r<=3'b111;
else
key_rst_r<=key_rst;
wire key_an;
assign key_an= (~key_rst_r)&(key_rst);
reg cnt;
always @(posedge clk or negedge rst_n)
if(!rst_n)
cnt<=20'd0;
else if(key_an)
cnt<=2'b0;
else
cnt<=cnt+1'b1;
reg low_sw;
always @(posedge clk or negedge rst_n )
if(!rst_n)
low_sw<=3'b111;
else if (cnt==2'b10)
low_sw<={sw3_n,sw2_n,sw1_n};
reg low_sw_r;
always @(posedge clk or negedge rst_n )
if(!rst_n)
low_sw_r<=3'b111;
else
low_sw_r<=low_sw;
wire led_ctrl;
assign led_ctrl=(~low_sw_r)&(low_sw);
reg d1;
reg d2;
reg d3;
always @(posedge clk or negedge rst_n )
if(!rst_n)
begin
d1<=1'b0;
d2<=1'b0;
d3<=1'b0;
end
else
begin
if(led_ctrl) d1<=~d1;
if(led_ctrl) d2<=~d2;
if(led_ctrl) d3<=~d3;
end
assign led_d3=d3?1'b1:1'b0;
assign led_d2=d2?1'b1:1'b0;
assign led_d1=d1?1'b1:1'b0;
endmodule
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