高手请进，帮忙看下程序哪错了~~
module rpg;regclock, red, amber, green;
parameteron=1, off=0, red_tics=350,
amber_tics=30,green_tics=200;
//交通灯初始化
initial red=off;
initial amber=off;
initial green=off;
//交通灯控制时序
always
begin
red=on; //开红灯
light(red,red_tics); //调用等待任务
green=on; //开绿灯
light(green,green_tics); //等待
amber=on; //开黄灯
light(amber,amber_tics); //等待
end
//定义交通灯开启时间的任务
task light(color,tics);
outputcolor;
input tics;
reg color;
begin
repeat(tics)@(posedge clock);//等待tics个时钟的上升沿
color=off;//关灯
end
endtask
//产生时钟脉冲的always块
always
begin
#100 clock=0;
#100 clock=1;
end
endmodule
我在Quartusii下编译的，下面是错误信息：
Error (10170): Verilog HDL syntax error at rpg.v(20) near text "color";expecting ")", or "inout", or "input", or "output", or "(*"
Error (10170): Verilog HDL syntax error at rpg.v(24) near text "begin";expecting an identifier ("begin" is a reserved keyword ), or "endmodule", or a parallel statement
Error (10112): Ignored design unit "rpg" at rpg.v(1) due to previous errors
Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings
Error: Peak virtual memory: 154 megabytes
Error: Processing ended: Mon Aug 23 14:12:02 2010
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error: Quartus II Full Compilation was unsuccessful. 5 errors, 0 warnings
哪里错了，麻烦高手解决下，小弟初学Verilog ，不是很懂~~谢谢 就没有人知道吗？ 在Quartusii下编译肯定是一堆错误啦，编译包括综合、优化和适配等，你的程序n多不可综合的，当然错了。拿到Modelsim里面仿真估计就没错了。。。 回复 3# 无名
嗯，谢谢啊
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