求大神 关于 VHDL 乘法
这是一个数乘以31的程序的源代码：LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult31 is
PORT
( clk :IN STD_LOGIC;
Din :IN SIGNED (10 DOWNTO 0);
Dout :OUT SIGNED (15 DOWNTO 0));
END mult31;
ARCHITECTURE a OF mult31 IS
SIGNAL s1 : SIGNED (15 DOWNTO 0);
SIGNAL s2 : SIGNED (10 DOWNTO 0);
SIGNAL s3 : SIGNED (15 DOWNTO 0);
BEGIN
P1:process(Din,s1,s2,s3)
BEGIN
s1<=DIN&"00000";
s2<=din;
if Din(10)='0' then
s3<=('0'&s1(14 downto 0))-("00000"&s2(10 DOWNTO 0));
else
s3<=('1'&s1(14 downto 0))-("11111"&s2(10 downto 0));
end if;
end process;
P2: PROCESS(clk,s3)
BEGIN
if clk'event and clk='1' then
Dout<=s3;
end if;
END PROCESS;
END a;
程序为什么可以利用这个完成乘以31的过程的？求大神解释解释啊
s1<=DIN&"00000";
s2<=din;
if Din(10)='0' then
s3<=('0'&s1(14 downto 0))-("00000"&s2(10 DOWNTO 0));
else
s3<=('1'&s1(14 downto 0))-("11111"&s2(10 downto 0));
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