大侠们，我要请教一个关于亚稳态的问题
大侠们，我要请教一个关于亚稳态的问题。module(input clk, input rstn, input signal, output signal_rising);reg signal_delay1;
reg signal_delay2;
always@(posedge clk or negedge rstn)
begin
if(rstn==0)
signal_delay1 <= 0;
else
signal_delay1 <= signal;
end
always@(posedge clk or negedge rstn)
begin
if(rstn==0)
signal_delay2 <= 0;
else
signal_delay2 <= signal_delay1;
end
assign signal_rising = (signal_delay1) & (~signal_delay2) ;
endmodule
这是一个扑捉上升沿的代码
Maverick(AI)(223476034)11:45:52
考虑到signal是异步的，所以用了两个触发器
最后assign signal_rising = (signal_delay1) & (~signal_delay2) ;
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