分频程序
哪位高手帮忙看一下，下面的程序是如何实现的entity divclk is
port(
clk : in std_logic; ------50MHZ
clk400 : out std_logic; -------400KHZ
scanclk : out std_Logic
);
end divclk;
architecture Behavioral of divclk is
begin
process(clk)
variable count : std_logic_vector(19 downto 0):=X"00000";
begin
if(rising_edge(clk))then
count:=count+1;
end if;
clk400<=count(2);
scanclk<=count(12);
end process;
end Behavioral;
如何从50MHZ分到400K的呢？
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