分频器里面可以进行加操作吗
分频器里面可以进行加操作吗？比如一个1:5000分频器，我用单片机发个数据让它加进去，编程总是无法实现程序如下：
module pwm1(dat,clkin,en,pwm1,pwm2,pwm3,clk,out);
input clk,clkin,en;
input dat;
outputpwm1,pwm2,pwm3;
outputout;
regbliang;
regzkb;
regzkb1;
regzkb2;
reg fpb;
reg fpb1;
reg fpb2;
regxwei;
regxwei1;
regxwei2;
regshuju;
reg adder;
reggdp;
regjs;
reggdp1;
regjs1;
reggdp2;
regjs2;
reg pwm_flag;
reg pwm_flag1;
reg pwm_flag2;
assign pwm1=pwm_flag;
assign pwm2=pwm_flag1;
assign pwm3=pwm_flag2;
assign out=bliang;
always @(posedge clkin)
begin
if(en==0)
begin
shuju= shuju>>1;
shuju = dat;
bliang=shuju;
end
elsebegin fpb=fpb;end
end
always @(posedgeen)
begin
case(shuju)
0:begin fpb=shuju; end
1:begin fpb1=shuju; end
2:begin fpb2=shuju;end
3:begin zkb=shuju;gdp<=fpb*zkb/100;end
4:begin zkb1=shuju;gdp1<=fpb1*zkb1/100;end
5:begin zkb2=shuju;gdp2<=fpb2*zkb2/100;end
6:begin xwei<=shuju; js<=js+fpb*xwei/360;end
default shuju<=shuju;
endcase
end
always@(posedge clk )
begin
if(js>=fpb)
beginjs<=0; end
else
begin js<=js+1; end
if(js<gdp)
beginpwm_flag=1; end
else beginpwm_flag=0;end
end
always@(posedge clk)
begin
if(js1>=fpb1)
begin js1<=0;end
else
begin js1<=js1+1; end
if(js1<gdp1)
begin pwm_flag1=1; end
else beginpwm_flag1=0;end
end
always@(posedge clk)
begin
if(js2>=fpb2)
begin js2<=0;end
else
begin js2<=js2+1; end
if(js2<gdp2)
begin pwm_flag2=1;end
else beginpwm_flag2=0;end
end
endmodule
结果总是出错：不能解决多重驱动 ！请问有没有什么好的解决办法啊！
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