rst_n,
clkin,
clkout
);
input rst_n;
input clkin;
output clkout;
reg clkout;
reg clk0,clk1,clk2;
reg clk0_reg,clk1_reg,clk2_reg;
reg c0;
reg c1,
reg c2;
reg c3;
always @(posedge clkin or negedge rst_n)
begin
if (!rst_n)
begin
clk0 <= 1'b0;
clk0_reg <= 1'b0;
c0 <= 8'd0;
end
else
begin
clk0_reg <= clk0;
if(c0 < 8'd200)
c0 <= c0 + 1'd1;
else
begin
clk0 <= ~clk0;
c0 <= 8'd0;
end
end
end
always @(posedge clkin or negedge rst_n)
begin
if (!rst_n)
begin
c1 <= 7'd0;
clk1 <= 1'b0;
clk1_reg <= 1'b0;
end
else
begin
clk1_reg <= clk1;
if(clk0 & (!clk0_reg))
begin
if(c1 < 8'd100)
c1 <= c1+1'b1;
else
begin
clk1 <= ~clk1;
c1 <= 7'd0;
end
end
end
end
always @(posedge clkin or negedge rst_n)
begin
if (!rst_n)
begin
c2 <= 7'd0;
clk2 <= 1'b0;
clk2_reg <= 1'b0;
end
else
begin
clk2_reg <= clk2;
if(clk1 & (!clk1_reg))
begin
if(c2 < 8'd100)
c2 <= c2 + 1'b1;
else
begin
clk2 <= ~clk2;
c2 <= 7'd0;
end
end
end
end
always @(posedge clkin or negedge rst_n)
begin
if (!rst_n)
begin
c3 <= 7'd0;
clk_out <= 1'b0;
end
else
begin
if(clk2 & (!clk2_reg))
begin
if(c3 < 4'd10)
c3 <= c3 + 1'b1;
else
begin
clk_out <= ~clk_out;
c3 <= 4'd0;
end
end
end
end
endmodule 路过……………… 我发了好几个分频器的帖子啊，找一下来看吧
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