错在哪？？？？？？？？？
module test11(clk,c1,c2,k1,k2,p1,p2);input clk;
output c1,c2;
output k1,k2;
output p1,p2;
wire shi1,shi2,gh;
wire time1,time2,time3,time4,time5,time6;
wire rst=1,k1=1,k2=1;
div16 cc(clk,rst,clk_16);
shijiana1(time1,time2,time3,time4,time5,time6,clk_16);
shaomiao b1(clk,c1,c1,c1,c1,c2,c2,c2,c2,time1,time2,time3,time4,time5,time6,shi1,shi2);
decode4_7 d1(p1,p1,p1,p1,p1,p1,p1,shi1,shi1,shi1,shi1);
decode4_7 d2(p2,p2,p2,p2,p2,p2,p2,shi2,shi2,shi2,shi2);
endmodule
module decode4_7(a,b,c,d,e,f,g,D3,D2,D1,D0);
outputa,b,c,d,e,f,g;
inputD3,D2,D1,D0;
reg a,b,c,d,e,f,g;
always @(D3 or D2 or D1 or D0)
begin
case({D3,D2,D1,D0})
4'd0:{a,b,c,d,e,f,g}=7'b1111110;
4'd1:{a,b,c,d,e,f,g}=7'b0110000;
4'd2:{a,b,c,d,e,f,g}=7'b1101101;
4'd3:{a,b,c,d,e,f,g}=7'b1111001;
4'd4:{a,b,c,d,e,f,g}=7'b0110011;
4'd5:{a,b,c,d,e,f,g}=7'b1011011;
4'd6:{a,b,c,d,e,f,g}=7'b1011111;
4'd7:{a,b,c,d,e,f,g}=7'b1110000;
4'd8:{a,b,c,d,e,f,g}=7'b1111111;
4'd9:{a,b,c,d,e,f,g}=7'b1111011;
default:{a,b,c,d,e,f,g}=7'b00000000;
endcase
end
endmodule
module shaomiao(clk,d0,d1,d2,d3,d4,d5,d6,d7,time1,time2,time3,time4,time5,time6,shi1,shi2);
input clk;
input time1,time2,time3,time4,time5,time6;
output d0,d1,d2,d3,d4,d5,d6,d7;
output shi1,shi2;
reg d0,d1,d2,d3,d4,d5,d6,d7;
reg shi1,shi2;
reg b;
always @(posedge clk) begin
if(b==4'd1111)
b=4'd0000;
else
b=b+1;
case(b)
3'd0:begin {d0,d1,d2,d3,d4,d5,d6,d7}=4'd00000001;shi1=time1;end
3'd1:begin {d0,d1,d2,d3,d4,d5,d6,d7}=4'd00000010;shi1=time2;end
3'd2:begin {d0,d1,d2,d3,d4,d5,d6,d7}=4'd00000100;shi1=time3;end
3'd3:begin {d0,d1,d2,d3,d4,d5,d6,d7}=4'd00001000;shi1=time4;end
3'd4:begin {d0,d1,d2,d3,d4,d5,d6,d7}=4'd00010000;shi2=time5;end
3'd5:begin {d0,d1,d2,d3,d4,d5,d6,d7}=4'd00100000;shi2=time6;end
3'd6:begin {d0,d1,d2,d3,d4,d5,d6,d7}=4'd01000000;shi2=4'd0000;end
3'd7:begin {d0,d1,d2,d3,d4,d5,d6,d7}=4'd10000000;shi2=4'd0000;end
endcase
end
endmodule
module div16(clk,rst,clk_16);
input clk,rst;
output clk_16;
reg count;
always @(posedge clk or negedge rst)
begin
if (!rst)
count <= 26'b0;
else
count <= count +1;
end
assign clk_16 = count;
endmodule
module shijian(time1,time2,time3,time4,time5,time6,clk);
output time1,time2,time3,time4,time5,time6;
input clk;
reg a,b,c,d,e,f;
reg time1,time2,time3,time4,time5,time6;
reg bb,cc,dd,ee,ff;
always @(posedge clk)
begin
if(a==4'd1010) begin
a=4'd0000; time1=a;bb=1; end
else begin
a=a+1; time1=a; bb=0;end
if(b==4'd0110) begin
b=4'd0000;time2=b;cc=1; end
else if(bb==1) begin
b=b+1;time2=b; cc=0;end
else begin
b=b;time2=b; cc=0;end
if(c==4'd1010) begin
c=4'd0000;time3=c;dd=1; end
else if(cc==1) begin
c=c+1;time3=c;dd=0;end
else begin
c=c;time3=c;dd=0;end
if(d==4'd0110) begin
d=4'd0000;time4=d;ee=1; end
else if(dd==1) begin
d=d+1;time4=d;ee=0;end
else begin
d=d;time4=d;ee=0;end
if(e==4'd1010) begin
e=4'd0000;time5=e;ff=1; end
else if(ee==1) begin
e=e+1;time5=e;ff=0;end
else begin
e=e;time5=e;ff=0;end
if(f==4'd0011) begin
f=4'd0000;time6=f; end
else if(ff==1) begin
f=f+1;time6=f;end
else begin
f=f;time6=f;end
end
endmodule
结果图
我原本想做一个时钟自加的
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