频率计信号控制源程序
频率计信号控制源程序module t_cont(clk_1hz,en,set,clr);
input clk_1hz;
output en,set,clr;
reg en;
wire set,clr;
reg en_temp;
always @(posedge clk_1hz)
en<=!en;
always @(negedge clk_1hz)
en_temp<=en;
assign set=!en & en_temp;
assign clr=!(en|en_temp);
endmodule
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