刚开始学ＶＨＤＬ～求助啊～～～
library ieee;use ieee.std_logic_1164.all;
entity fsq is
port
(
clk : in std_logic;
u : out std_logic
);
end fsq;
architecture afsq of fsq is
signal p : std_logic_vector(3 downto 0);
signal p0 : std_logic;
signal p1 : std_logic;
signal p2 : std_logic;
signal p3 : std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then
p0<=not p0;
end if;
end process;
process(p0)
begin
if p0'event and p0='0' then
p1<=not p1;
end if;
end process;
process(p1)
begin
if p1'event and p1='0' then
p2<=not p2;
end if;
end process;
process(p2)
begin
if p2'event and p2='0' then
p3<=not p3;
end if;
end process;
p<=p3&p2&p1&p0;
process(p)
begin
if p="1000" then
p<="0000";
end if;
case p is
when "0000" => u<='0';
when "0001" => u<='1';
when "0010" => u<='1';
when "0011" => u<='0';
when "0100" => u<='1';
when "0101" => u<='1';
when "0110" => u<='1';
when "0111" => u<='1';
when others => null;
end case;
end process;
end afsq;
这个是我的程序。。刚开始学VHDL，我想做一个01101111序列发生器。。这么写就会提示1 errors：signal "p" has multiple sources。。。怎么改？ P的用法啊,p<=p3&p2&p1&p0,P是一个组合，P3,P2,P1这些都只是一个数，这个&是与的意思吗？我觉得不能当拼接来用吧。。。不太懂，我是学Verilog的。..求高手 好好看看VHDL语法吧。一个信号多驱动源了。vhdl是不支持对一个信号进行多重驱动。 p<=p3&p2&p1&p0;
这里的p变为signal p_i 试试吧
呵呵，很有想象力的程序。 路过,挣分....... 建议你改用变量，在进程中变量比较好用。signal "p" has multiple sources。。。是不是指p为赋初值0
，1均有可能。
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