写了一个用74HC163为底层元件的19进制计数器 帮忙看看哪有问题啊？？？
library ieee;use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity s41 is --底层实体1
port(
clk1,enp1,ent1,ld1,cr1:in std_logic;
d1: in unsigned(3 downto 0);
q1:out unsigned(3 downto 0);
co1: out std_logic);
end s41;
architecture s41a of s41 is
signal iq:unsigned(3 downto 0):="1101";
--signal fc:bit:=1;
begin
process(clk1,enp1,ent1,ld1,cr1,d1)
begin
q1<=iq;
if(clk1'event and clk1='1' )then
if(ld1='0')then
iq<=d1;
elsif(cr1='0')then
iq<=(others=>'0');
elsif (ent1 and enp1)='1' then
iq<=iq+1;
end if;
if(iq=15) and (ent1='1')then
co1<='1';
else
co1<='0';
end if;
q1<=iq;
end if;
end process;
ends41a;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity s42 is --底层实体2
port(
clk2,enp2,ent2,ld2,cr2:in std_logic;
d2: in unsigned(3 downto 0);
q2:out unsigned(3 downto 0);
co2: out std_logic);
end s42;
architecture s42a of s42 is
signal iq:unsigned(3 downto 0):="1110";
--signal nco:std_logic;
begin
process(clk2,enp2,ent2,ld2,cr2,d2)
begin
q2<=iq;
if(clk2'event and clk2='1' )then
if(ld2='0')then
iq<=d2;
elsif(cr2='0')then
iq<=(others=>'0');
elsif (ent2 and enp2)='1' then
iq<=iq+1;
end if;
if(iq=15 )and (ent2='1')then
co2<='1';
else
co2<='0';
end if;
q2<=iq;
end if;
end process;
ends42a;
library ieee;
use ieee.std_logic_1164.all;
entity nt is --底层实体3
port(
y:in std_logic;
z:out std_logic);
end nt;
architecture nta of nt is
begin
process(y)
begin
z<=not y;
end process;
endnta;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
entity s4 is --top
port(
cp,enp,ent,ld,cr:in std_logic;
dd: in unsigned(7 downto 0);--:="11011110";
qo:out unsigned(4 downto 0));
end s4;
architecture s19s of s4 is
signal a,b,c,d:std_logic;
component s41
port(
clk1,enp1,ent1,ld1,cr1:in std_logic;
d1: in unsigned(3 downto 0);
q1:out unsigned(3 downto 0);
co1: out std_logic);
end component;
component s42
port(
clk2,enp2,ent2,ld2,cr2:in std_logic;
d2: in unsigned(3 downto 0);
q2:out unsigned(3 downto 0);
co2: out std_logic);
end component;
component nt
port(
y:in std_logic;
z:out std_logic);
end component;
begin
G1:s41 port map
(clk1=>cp,
enp1=>'1',
ent1=>'1',
cr1=>'1',
co1=>a,
ld1=>c,
q1(0)=>qo(0),
q1(1)=>qo(1),
q1(2)=>qo(2),
q1(3)=>qo(3),
d1(0)=>dd(4),
d1(1)=>dd(5),
d1(2)=>dd(6),
d1(3)=>dd(7)
);
G2:s42 port map
(clk2=>cp,
enp2=>a,
ent2=>a,
cr2=>'1',
co2=>d,
ld2=>c,
q2(0)=>qo(4),
d2(0)=>dd(0),
d2(1)=>dd(1),
d2(2)=>dd(2),
d2(3)=>dd(3)
);
G3:nt port map
(y=>d,
z=>c
);
end s19s; 还在计数器这徘徊呢。。。Verilog的计数器我上传了好几个，当参考吧
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