错在那里？？？？？？？？？？？？？？？？？？？？？？？？？？？？？
module clock(clk,
rst,
point,
take1,
take2,
seven1,
seven2
);
input clk;//时钟50MHz
input rst;//复位
output point;//两个动态七管LED的右下点
output take1;//第一个动态七管LED的使动端
output take2;//第二个动态七管LED的使动端
output seven1;//第一个动态七管LED的数据输入端
output seven2;//第二个动态七管LED的数据输入端
reg point=2'd0;
wire clk_1Hz,clk_250Hz,time1,time2,time3,time4,time5,time6;
wire digital1,digital2,digital3,digital4,digital5,digital6,
digital_out1,digital_out2;
assign time1=clk_1Hz;
clock_1Hzclk1(clk,rst,clk_1Hz);
PLL clk250(clk,rst,clk_250Hz);
div_10 clkto1(time1,rst,time2);//1Hz-->1/10Hz
div_6 clkto2(time2,rst,time3);//1/10Hz-->1/60Hz
div_10 clkto3(time3,rst,time4);//1/60Hz-->1/600Hz
div_6 clkto4(time4,rst,time5);//1/600Hz-->1/3600Hz
div_10 clkto5(time5,rst,time6);//1/3600Hz-->1/36000Hz
plus10 digitalto1(time1,rst,digital1);//产生秒钟个位
plus6 digitalto2(time2,rst,digital2);//产生秒钟十位
plus10 digitalto3(time3,rst,digital3);//产生分钟个位
plus6 digitalto4(time4,rst,digital4);//产生分钟十位
plus10 digitalto5(time5,rst,digital5);//产生时钟个位
plus6 digitalto6(time6,rst,digital6);//产生时钟十位
shaomiao putout(clk_250Hz,rst,digital1,digital2,digital3,digital4,digital5,digital6,
digital_out1,digital_out2,take1,take2); //扫描数码管，并赋值
decode4_7 led1(seven1,seven1,seven1,seven1,seven1,seven1,seven1,digital_out1,digital_out1,digital_out2,digital_out2);
decode4_7 led2(seven2,seven2,seven2,seven2,seven2,seven2,seven2,digital_out2,digital_out2,digital_out1,digital_out1);
endmodule
//------------------------------------------------------------------------------
module decode4_7(
a,
b,
c,
d,
e,
f,
g,
D3,
D2,
D1,
D0
);
//
outputa,b,c,d,e,f,g;
inputD3,D2,D1,D0;
//七管LED转换程序
reg a,b,c,d,e,f,g;
always @(D3 or D2 or D1 or D0)
begin
case({D3,D2,D1,D0})
4'd0:{a,b,c,d,e,f,g}=7'b1111110;
4'd1:{a,b,c,d,e,f,g}=7'b0110000;
4'd2:{a,b,c,d,e,f,g}=7'b1101101;
4'd3:{a,b,c,d,e,f,g}=7'b1111001;
4'd4:{a,b,c,d,e,f,g}=7'b0110011;
4'd5:{a,b,c,d,e,f,g}=7'b1011011;
4'd6:{a,b,c,d,e,f,g}=7'b1011111;
4'd7:{a,b,c,d,e,f,g}=7'b1110000;
4'd8:{a,b,c,d,e,f,g}=7'b1111111;
4'd9:{a,b,c,d,e,f,g}=7'b1111011;
default:{a,b,c,d,e,f,g}=7'b00000000;
endcase
end
endmodule
//---------------------------------------------------------------
module clock_1Hz(
//时钟转换
clk,//时钟
rst,
clk_1Hz
);
input clk;
input rst;
output clk_1Hz;
reg clk_1Hz;
reg count_26;
always @(posedge clk or negedge rst)
begin
if(!rst)
count_26<=26'd0;
else if(count_26==26'd26214000)
begin
count_26<=26'd0;
clk_1Hz<=~clk_1Hz;
end
else
count_26<=count_26+26'd1;
end
endmodule
//------------------------------------------------------------------
module PLL(clk,rst,clk_250Hz);
//时钟转换
input clk,rst;
output clk_250Hz;
reg clk_250Hz;
reg count_div_4;
always @(posedge clk or negedge rst)
begin
if(!rst)
count_div_4<=26'd0;
else if(count_div_4==26'd9999)
begin
count_div_4<=26'd0;
clk_250Hz<=~clk_250Hz;
end
else
count_div_4<=count_div_4+26'd1;
end
endmodule
//---------------------------------------------------------------------------
module div_10(
//十分频
clk_in,//时钟
rst,
clk_out
);
input clk_in;
input rst;
output clk_out;
reg clk_out;
reg count_5;
always @(posedge clk_in or negedge rst)
begin
if(!rst)
count_5<=4'd0;
else if(count_5==4'd5)
begin
count_5<=4'd0;
clk_out=~clk_out;
end
else
count_5<=count_5+4'd1;
end
endmodule
//-------------------------------------------------------------
module div_6(
//六分频
clk_in,//时钟
rst,
clk_out
);
input clk_in;
input rst;
output clk_out;
reg clk_out;
reg count_3;
always @(posedge clk_in or negedge rst)
begin
if(!rst)
count_3<=4'd0;
else if(count_3==4'd3)
begin
count_3<=4'd0;
clk_out=~clk_out;
end
else
count_3<=count_3+4'd1;
end
endmodule
//---------------------------------------------
module shaomiao(
//扫描程序
clk,
rst,
digital_in1,
digital_in2,
digital_in3,
digital_in4,
digital_in5,
digital_in6,
digital_out1,
digital_out2,
take1,
take2
);
input clk;//时钟
input rst;
input digital_in1;//秒钟个位
input digital_in2;//秒钟十位
input digital_in3;//分钟个位
input digital_in4;//分钟十位
input digital_in5;//时钟个位
input digital_in6;//时钟十位
output digital_out1,take1;
output digital_out2,take2;
reg digital_out1,digital_out2,take1,take2;
reg count_8;
always @(posedge clk or negedge rst)
begin
if(!rst)
count_8<=4'd0;
else if(count_8==4'd8)
count_8<=4'd0;
else
count_8<=count_8+4'd1;
case(count_8)
4'd0 : begin digital_out1<=digital_in1;
{take1,take2}=8'b00000001;
end
4'd1 : begin digital_out1<=digital_in2;
{take1,take2}=8'b00000010;
end
4'd2 : begin digital_out1<=digital_in3;
{take1,take2}=8'b00000100;
end
4'd3 : begin digital_out1<=digital_in4;
{take1,take2}=8'b00001000;
end
4'd4 : begin digital_out2<=digital_in5;
{take1,take2}=8'b00010000;
end
4'd5 : begin digital_out2<=digital_in6;
{take1,take2}=8'b00100000;
end
4'd6 : begin digital_out2<=4'd0;
{take1,take2}=8'b01000000;
end
4'd7 : begin digital_out2<=4'd0;
{take1,take2}=8'b10000000;
end
endcase
end
endmodule
//-------------------------------------------------------------------
module plus10(
//不断加1，到10归0
clk,//时钟
rst,
digitalt
);
input clk,rst;
output digitalt;
reg digital;
always @(posedge clk or negedge rst)
begin
if(!rst)
digital<=4'd0;
else if(digital==4'd9)
digital<=4'd0;
else
digital=digital+4'd1;
end
assign digitalt=digital;
endmodule
//-------------------------------------------------------------------------
module plus6(
//不断加1，到6归0
clk,//时钟
rst,
digital
);
input clk,rst;
output digital;
reg digital;
always @(posedge clk or negedge rst)
begin
if(!rst)
digital<=4'd0;
else if(digital==4'd5)
digital<=4'd0;
else
digital=digital+4'd1;
end
endmodule
这是一个数码管程序，运行时不对，逢10进1，变成逢3进1 听说在一个工程里不可以使用相同的变量命名。。。 变量是可以的，只是文件名不能而已吧，你程序太长了，我最近没时间看 太长了，你觉得哪有问题发一下，别都发上来啊。 不可能让别人帮你把整个程序仿真，然后一步步找结果的啊
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