[讨论] RS232串口程序
源代码：module urat(clock, rxd, RxD_data_ready, sbuf, RxD_endofpacket, RxD_idle);
input clock, rxd;
output RxD_data_ready; // onc clock pulse when RxD_data is valid
output sbuf;
parameter ClkFrequency = 50000000; // 25MHz
parameter Baud = 9600;
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high)
output RxD_idle; // no data is being received
// Baud generator (we use 8 times oversampling)
parameter Baud8 = Baud*8;
parameter Baud8GeneratorAccWidth = 16;
wire Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
reg Baud8GeneratorAcc;
always @(posedge clock) Baud8GeneratorAcc <= Baud8GeneratorAcc + Baud8GeneratorInc;
wire Baud8Tick = Baud8GeneratorAcc;
////////////////////////////
reg RxD_sync_inv;
always @(posedge clock) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv, ~rxd};
// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup
reg RxD_cnt_inv;
reg RxD_bit_inv;
always @(posedge clock)
if(Baud8Tick)
begin
if( RxD_sync_inv && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 2'h1;
else
if(~RxD_sync_inv && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 2'h1;
if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 1'b0;
else
if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1'b1;
end
reg state;
reg bit_spacing;
// "next_bit" controls when the data sampling occurs
// depending on how noisy the RxD is, different values might work better
// with a clean connection, values from 8 to 11 work
wire next_bit = (bit_spacing==4'd10);
always @(posedge clock)
if(state==0)
bit_spacing <= 4'b0000;
else
if(Baud8Tick)
bit_spacing <= {bit_spacing + 4'b0001} | {bit_spacing, 3'b000};
always @(posedge clock)
if(Baud8Tick)
case(state)
4'b0000: if(RxD_bit_inv) state <= 4'b1000; // start bit found?
4'b1000: if(next_bit) state <= 4'b1001; // bit 0
4'b1001: if(next_bit) state <= 4'b1010; // bit 1
4'b1010: if(next_bit) state <= 4'b1011; // bit 2
4'b1011: if(next_bit) state <= 4'b1100; // bit 3
4'b1100: if(next_bit) state <= 4'b1101; // bit 4
4'b1101: if(next_bit) state <= 4'b1110; // bit 5
4'b1110: if(next_bit) state <= 4'b1111; // bit 6
4'b1111: if(next_bit) state <= 4'b0001; // bit 7
4'b0001: if(next_bit) state <= 4'b0000; // stop bit
default: state <= 4'b0000;
endcase
reg sbuf;
always @(posedge clock)
if(Baud8Tick && next_bit && state) sbuf <= {~RxD_bit_inv, sbuf};
reg RxD_data_ready, RxD_data_error;
always @(posedge clock)
begin
RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received
RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 && RxD_bit_inv); // error if the stop bit is not received
end
reg gap_count;
always @(posedge clock) if (state!=0) gap_count<=5'h00; else if(Baud8Tick & ~gap_count) gap_count <= gap_count + 5'h01;
assign RxD_idle = gap_count;
reg RxD_endofpacket; always @(posedge clock) RxD_endofpacket <= Baud8Tick & (gap_count==5'h0F);
endmodule RS232串口程序 我用的vhdl，这个不怎么看得懂。:'( 我也看不懂啊？？？？？？ 这个可以做20个串口吗？ 希望可以用 谢谢大佬分享
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