`include使用问题
//------------------sys.v-------------------------`include"E:\FPGA\Quartus\shiyanlianxi\shiyan10_1\p_to_s.v"
`include"E:\FPGA\Quartus\shiyanlianxi\shiyan10_2\s_to_p.v"module system(D_in, T0, T1, data, D_out, SEND, ESC,
DSC,TAKE, ADD_100, ADD_101);
input D_out, SEND, ESC, DSC, TAKE, ADD_100, ADD_101;
inout data;
output D_in, T0, T1;
p_to_sp_to_s(.D_in(D_in),.T0(T0),.data(data),
.SEND(SEND),.ESC(ESC),.ADD_100(ADD_100));
s_to_ps_to_p(.T1(T1),.data(data),.D_out(D_out),
.DSC(DSC),.TAKE(TAKE),.ADD_101(ADD_101));
endmodule 会报错，是什么原因啊，请教各位大哥。
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