累加器verilog语言编程问题
刚刚接触FPGA，编程方面也不是很擅长。今天做了一个累加器的verilog编程，仿真波形图一直出错，想请大神指教一下错误的原因，十分感谢！我要实现的累加器功能是：连续输入几百个gary_value，每满15个gary_value输出一个累加结果，同时累加器清零。我写的代码如下：
module accumulator (clk, rst_n,a_en,gary_value,accumulation);
input clk, rst_n;
input a_en;//累加启动使能，高有效
input gary_value;
output accumulation;
reg accum_i;
reg accum_k;
reg accumulation;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
accum_k <= 0;
accum_i <= 0;
end
else if(a_en)
begin
if(accum_k==8'd16)
begin
accumulation <= accum_i;
accum_i <= 0;
accum_k <= 0;
end
else if(accum_k!=8'd16)
begin
accum_i <= accum_i + gary_value;
accum_k <= accum_k+1;
end
else
accum_k <= 0;
end
end
endmodule
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