verilog调用函数出现问题，求高手帮忙
module yunsuan1(clk,n,result,reset);input clk,reset;
input n;
output result;
reg result;
always@(posedge clk) begin
if(!reset)
begin
result<=0;
end
else
begin
result<=myfouc(n);
end
end
function myfouc;
input ina;
reg temp;
begin
myfouc=ina?1:0;//if ina!=0,myfouc=1;
//for(temp=2;temp<=ina;temp=temp+1)
//myfouc=temp*myfouc;
temp=2;
while(temp<=ina)
begin
myfouc=temp*myfouc;
temp=temp+1;
end
end
endfunction
endmodule
编译时会出现 Error (10119): Verilog HDL Loop Statement error at yunsuan1.v(24): loop with non-constant loop condition must terminate within 250 iterations
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