美国IC设计公司招人
公司从事多媒体及宽带通讯系统级芯片 (SOC) 设计的美国高科技企业。所研发生产的各类芯片大量地被思科，北电，朗讯，阿尔卡特，华为，联想等使用。主要产品包括宽带有线网络通讯，3G无线通讯基站以及多媒体电子领域的一系列模拟与数字系统级芯片。主要设计基于深亚微米CMOS及SiGe生产工艺，采用以系统集成为主，模拟与数字电路相结合的前沿设计思路。与世界及亚洲知名IT和通讯公司紧密合作，具有巨大的发展潜力。奖金及具吸引力的工资福利待遇,公司力争给投资人和员工以最大利益的回报。现招聘两个职位：
Sr. Analog IC Design Engineer (US-San Diego or Shanghai)
Responsibilities:
1.Design state of the art analog and mixed signal circuits for VLSI integration.
2.Assist in defining functional and performance requirements.
3.Assist product definition including specification, partitioning, architecture, project scheduling, tracking and resource estimations.
4.Design custom analog and mixed signal blocks
(for example, CMOS include very high performance ADCs, DACs, PLLs and signal conditioning circuits)
5.Verification of performance requirements using appropriate simulation and verification tools.
6.Validate and debug silicon in the lab
Requirement:
1.Have proven track record in the successful design and physical implementation of high performance
2.High speed A/D and D/A converters, from concept to product introduction.
Required Skills:
Experience and Qualifications Required:
MSEE or equivalent. Transistor level circuit design in sub-micron CMOS. Types of circuits/systems designed are PLLs, VCOs, Mixers, Filters, Amplifiers, modulators, A/Ds, D/As, OP AMPs and references. Must have hands on experience using analog, mixed mode tools for schematic entry, layout entry/LVS and DRC verification.Practical lab debug experience and a proven track record in design and bringing to production of high performance A/D's and D/A's is HIGHLY desirable
R&D Analog Design Lead
Description:
Lead a Physical Design Team through the complete SOC backend flow and will be working on IO Processor/IO translator System-on-a-Chip (SoC) development projects.
Responsibilities:
Build and lead analog design group to do analog circuit design for communication, multi-media and consumer product.
Requirement:
1.BSEE/MSEE with experience ranging from 7-12 years
2.Having at least been involved in physical design for two to three multi-million Gate Count ASIC or mixed-signal projects from net-list to Tape-out.
3.Proven Experience with one of the standard flows using Synopsys /Cadence/Magma.
4.Ancillary scripting skills like Perl/ Tcl-Tk/Awk highly desirable.
5.Ability to work as a part of a global cross-site team
6.Strong English and Chinese Verbal and Written Communication Skills
7.With experience for following product type is a plus:
- Synthesis and Static Timing Analysis using Synopsys-DC or Primetime.
- Formal Verification using Verplex-LEC or Formality.
- Floor-Planning, P & R
- Physical Verification/DRC/LVS.
- Power grid/IR/Clock Tree/Xtalk analysis and fix
- High performance analog macro block layout such as ADCs, DACs, PORs, PLLs and ESD padrings.
请有意者通过下列方式和我联系：
Richard Xing
Tel: 021-51337532
msn: stalen1@msn.com
email: richard.xing@agconsultant.net 6
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