如何用verilog写异步的fifo
我想写一个FIFO，异步的，写时钟是64K，读时钟是256K，输入的信号是是64Kbit/s,自己写了一个程序，但仿真出来 不对，数据 出来应该是压缩的才对，即压缩成原来的1/4，大家帮看看该怎么写。module myfifo2(clk_1,indata,clk_2,outdata);
input clk_1; //write clock//
input indata; //input data//
input clk_2; //readclock//
output outdata; // output data//
parameter DEPTH=256,MAX_COUNT=8'b11111111; //256*1//
reg emptyp=1'b1; //empty flag//
reg fullp=1'b0; //fullflag//
reg outdata;
regtail=8'b00000000; //tail pointer//
reghead=8'b00000000; //head pointer//
reg fifomem; //define the memory//
integer COUNT_1=0;
integer COUNT_2=0;
//write//
always @(posedge clk_1 )
if(emptyp==1'b1)
begin fifomem<=indata;
end
//read//
always @(posedgeclk_2)
if(fullp==1'b1)
beginoutdata<=fifomem;
end
//update the head register//
always @(posedge clk_1)begin
if(emptyp==1'b1)begin
head<=head+1;
end
end
//update the tail register//
always @(posedge clk_2)begin
if(fullp==1'b1) begin
tail<=tail+1; end
end
//update the count regsiter//
always @(posedge clk_1)
if(emptyp==1'b1) begin
if(COUNT_1!=MAX_COUNT) begin
COUNT_1<=COUNT_1+1;end
else COUNT_1=0; end
always @( posedge clk_2)
if(fullp<=1'b1) begin
if(COUNT_2!=MAX_COUNT) begin
COUNT_2<=COUNT_2+1;end
else COUNT_2=0; end
// update the flags//
always @( COUNT_1) begin
if(COUNT_1==DEPTH-1) begin
emptyp<=1'b0; end
else
emptyp<=1'b1 ; end
always @(COUNT_2) begin
if(COUNT_2==DEPTH-1) begin
fullp<=1'b0; end
else
fullp<=1'b1; end
endmodule
这个不太清楚了 谢谢楼主的分享 学习学习学习 课程设计--电梯控制器
http://www.fpgaw.com/forum.php?mod=viewthread&tid=1689&fromuid=54563
(出处: fpga论坛|fpga设计论坛)
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