lcytms 发表于 2016-10-12 23:04:00

解决仿真问题Error: (vsim-19) Failed to access library 。。。

本帖最后由 lcytms 于 2016-10-14 11:40 编辑

解决仿真问题Error: (vsim-19) Failed to access library 。。。


在使用Quartus II 13.0自带modelsim-altera对DDS程序进行仿真时报错，而使用外部modelsim正常。
查找这个问题，花了近2天时间，进行了各种百度。
最终在大牛的指点下解决。解决的方法很简单，就是修改环境变量，去掉原有的 变量modelsim    值D:\modeltech64_10.2\modelsim.ini 这一项。
然后重启Quartus，自带modelsim-altera即恢复正常工作。




lcytms 发表于 2016-10-12 23:06:33

报错信息

# Loading work.DDS_tb
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_ver' at "./verilog_libs/altera_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/lpm_ver' at "./verilog_libs/lpm_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/sgate_ver' at "./verilog_libs/sgate_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_mf_ver' at "./verilog_libs/altera_mf_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_lnsim_ver' at "./verilog_libs/altera_lnsim_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/cycloneive_ver' at "./verilog_libs/cycloneive_ver".
#
# No such file or directory. (errno = ENOENT)
# Loading work.DDS
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_ver' at "./verilog_libs/altera_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/lpm_ver' at "./verilog_libs/lpm_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/sgate_ver' at "./verilog_libs/sgate_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_mf_ver' at "./verilog_libs/altera_mf_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_lnsim_ver' at "./verilog_libs/altera_lnsim_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/cycloneive_ver' at "./verilog_libs/cycloneive_ver".
#
# No such file or directory. (errno = ENOENT)
# Loading work.DDS_controller
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_ver' at "./verilog_libs/altera_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/lpm_ver' at "./verilog_libs/lpm_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/sgate_ver' at "./verilog_libs/sgate_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_mf_ver' at "./verilog_libs/altera_mf_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_lnsim_ver' at "./verilog_libs/altera_lnsim_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/cycloneive_ver' at "./verilog_libs/cycloneive_ver".
#
# No such file or directory. (errno = ENOENT)
# Loading work.rom
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_ver' at "./verilog_libs/altera_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/lpm_ver' at "./verilog_libs/lpm_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/sgate_ver' at "./verilog_libs/sgate_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_mf_ver' at "./verilog_libs/altera_mf_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_lnsim_ver' at "./verilog_libs/altera_lnsim_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/cycloneive_ver' at "./verilog_libs/cycloneive_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-3033) D:/ZXOPEN2016/class/DDS/rom.v(81): Instantiation of 'altsyncram' failed. The design unit was not found.
#
#         Region: /DDS_tb/dut/rom1
#         Searched libraries:
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_ver' at "./verilog_libs/altera_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/lpm_ver' at "./verilog_libs/lpm_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/sgate_ver' at "./verilog_libs/sgate_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_mf_ver' at "./verilog_libs/altera_mf_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/altera_lnsim_ver' at "./verilog_libs/altera_lnsim_ver".
#
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library './verilog_libs/cycloneive_ver' at "./verilog_libs/cycloneive_ver".
#
# No such file or directory. (errno = ENOENT)
#             D:/ZXOPEN2016/class/DDS/simulation/modelsim/rtl_work
#             D:/ZXOPEN2016/class/DDS/simulation/modelsim/rtl_work
#             D:/ZXOPEN2016/class/DDS/simulation/modelsim/rtl_work
# Error loading design
# Error: Error loading design
#      Pausing macro execution
# MACRO ./DDS_run_msim_rtl_verilog.do PAUSED at line 14

lcytms 发表于 2016-10-12 23:20:23

本帖最后由 lcytms 于 2016-10-14 13:33 编辑

排错过程：

        大牛打开自带modelsim-altera，新建工程时发现modelsim.ini指向了独立modelsim的对应文件D:/modeltech64_10.2/modelsim.ini，而不是自带modelsim-altera的对应文件D:/altera/13.0/modelsim_ase/modelsim.ini。
        此时并没有想到去删除环境变量中那一项。
        大牛先用自带modelsim-altera打开DDS 项目，进行仿真，观察liabray发现缺少各种文件，总之又在工程里面添加了一个altera_mf.v文件后，仿真成功。
        再来解决跨平台仿真的问题。
        先是尝试在自带modelsim-altera下能不能修改设置，经过各种尝试没有找到修改的入口。
        经过种种考虑，决定试着删除删除环境变量中那一项，结果一试成功。可喜可贺！

泛爱不懂 发表于 2016-10-14 10:09:56

恭喜啊，这个方法很实用啊

韩辰 发表于 2017-2-13 10:01:21

很好地一种解决思路，谢谢

zxopenhl 发表于 2017-2-13 13:38:15

可以让我们初学者少走很多弯路，不错！

zxopenljx 发表于 2025-2-28 16:19:51

解决仿真问题Error: (vsim-19) Failed to access library
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