集成电路技术分享 - Powered by Discuz! Archiver

lcytms 发表于 2017-4-13 21:05:15

北理工选修课第十四课 VGA（DDS波形显示）

本帖最后由 lcytms 于 2017-4-13 21:07 编辑

北理工选修课第十四课
VGA（DDS波形显示）

从2017年2月27日起，至芯科技承担连续8周的北理工选修课任务，每周4课时。
选修学生为计算机专业大三学生，人数约100人。
在此同步发布上课讲义，谨供参考。

lcytms 发表于 2017-4-13 21:09:23

附件为20170413讲义
（北理工选修课第十四课 VGA（DDS波形显示））

小舍YZ 发表于 2017-4-14 12:10:02

谢谢分享。。。。。。。。。。。。。。:lol:lol:lol

粪斗的孩 发表于 2017-4-22 15:47:00

谢谢分享楼主

gnifengyu 发表于 2017-5-3 16:21:25

不错，谢谢了

lcytms 发表于 2018-3-1 22:31:59

节日快乐！！！

Sure 发表于 2018-3-2 18:05:02

下载查看

yangjie1993 发表于 2018-11-20 22:11:40

老师，看过您在腾讯课堂的课，现在遇到一些问题，请问可以帮忙看看问题在哪嘛？谢谢见帖子
请问我这个o_wave为什么没有波形？定义输入是时钟复位和按键，输出数码管显示和VGA观察。谢谢

yangjie1993 发表于 2018-11-20 22:13:43

module top (clk, rst_n, key, r, g, b, sel,seg,hsync, vsync, VGA_CLK, VGA_BLANK, VGA_SYNC);

input clk, rst_n;
input key;

output sel;
output seg;
output r, g;
output b;
output hsync, vsync;
output VGA_CLK;
output VGA_BLANK, VGA_SYNC;

assign VGA_BLANK = 1'b1;
assign VGA_SYNC = 1'b0;

wire key_out;
wire rgb;
wire addr;
wire sine_q, square_q,triangle_q;
wire o_wave;
wire data;

//parameter T20ms = 800_000;

pll pll(
.areset(~rst_n),
.inclk0(clk),
.c0(VGA_CLK)
); // VGA_CLK is 40M clock

jitter_key k0(
.clk(VGA_CLK),
.rst_n(rst_n),
.key_in(key),
.key_out(key_out)
);

jitter_key k1(
.clk(VGA_CLK),
.rst_n(rst_n),
.key_in(key),
.key_out(key_out)
);

jitter_key k2(
.clk(VGA_CLK),
.rst_n(rst_n),
.key_in(key),
.key_out(key_out)
);

sin_8x256 sin_8x256_inst (
.address ( addr ),
.clock ( VGA_CLK ),
.q ( sine_q )
);

squ_8x256 squ_8x256_inst (
.address ( addr ),
.clock ( VGA_CLK ),
.q ( square_q )
);

tri_8x256 tri_8x256_inst (
.address ( addr ),
.clock ( VGA_CLK ),
.q ( triangle_q )
);

dds_controller ctrl(
.clk(VGA_CLK),
.rst_n(rst_n),
.key_out(key_out),
.addr(addr),
.sine_q(sine_q),
.square_q(square_q),
.triangle_q(triangle_q),
.o_wave(o_wave),
.data(data)
);

seg7 seg7(
.clk (clk),
.rst_n(rst_n),
.data (data),
.sel (sel),
.seg (seg)
);

vga_dds vga_dds (
.clk(VGA_CLK),
.rst_n(rst_n),
.key_out(key_out),
.wave(o_wave),
.rgb8(rgb),
.hsync(hsync),
.vsync(vsync)
);

rgb8 rgb8 (
.rgb8(rgb),
.r(r),
.g(g),
.b(b)
);

endmodule
下面是tb
`timescale 1ns/1ps

module top_tb;

reg clk, rst_n;
reg key;

wire sel;
wire seg;
wire r, g;
wire b;
wire hsync, vsync;
wire VGA_CLK;
wire VGA_BLANK, VGA_SYNC;

reg seg_monitor;

top dut (
.clk(clk),
.rst_n(rst_n),
.key(key),
.sel(sel),
.seg(seg),
.r(r),
.g(g),
.b(b),
.hsync(hsync),
.vsync(vsync),
.VGA_CLK(VGA_CLK),
.VGA_BLANK(VGA_BLANK),
.VGA_SYNC(VGA_SYNC)
);

initial
begin
clk = 1;
rst_n = 0;
key=3'b111;
#200.1
rst_n = 1;

#28000 key = 3'b101; #2000 key = 3'b111;//key，切换频率
#28000 key = 3'b101; #2000 key = 3'b111;
/*#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;*/

#28000 key = 3'b011; #2000 key = 3'b011;//key，切换振幅
#28000 key = 3'b011; #2000 key = 3'b011;
#28000 key = 3'b011; #2000 key = 3'b011;
#28000 key = 3'b011; #2000 key = 3'b011;

#28000 key = 3'b110; #2000 key = 3'b111;//key，切换波形

#28000 key = 3'b101; #2000 key = 3'b111;//key，切换频率
#28000 key = 3'b101; #2000 key = 3'b111;
/*#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;*/

#28000 key = 3'b011; #2000 key = 3'b011;//key，切换振幅
#28000 key = 3'b011; #2000 key = 3'b011;
#28000 key = 3'b011; #2000 key = 3'b011;
#28000 key = 3'b011; #2000 key = 3'b011;

#28000 key = 3'b110; #2000 key = 3'b111;//key，切换波形

#28000 key = 3'b101; #2000 key = 3'b111;//key，切换频率
#28000 key = 3'b101; #2000 key = 3'b111;
/*#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;
#28000 key = 3'b101; #2000 key = 3'b111;*/

#28000 key = 3'b011; #2000 key = 3'b011;//key，切换振幅
#28000 key = 3'b011; #2000 key = 3'b011;
#28000 key = 3'b011; #2000 key = 3'b011;
#28000 key = 3'b011; #2000 key = 3'b011;

#30_000 $stop;
end

always #10 clk = ~clk;

always @(*)
begin
case(seg)
8'b1100_0000 : seg_monitor = "0" ;//0
8'b1111_1001 : seg_monitor = "1" ;//1
8'b1010_0100 : seg_monitor = "2" ;//2
8'b1011_0000 : seg_monitor = "3" ;//3
8'b1001_1001 : seg_monitor = "4" ;//4
8'b1001_0010 : seg_monitor = "5" ;//5
8'b1000_0010 : seg_monitor = "6" ;//6
8'b1111_1000 : seg_monitor = "7" ;//7
8'b1000_0000 : seg_monitor = "8" ;//8
8'b1001_0000 : seg_monitor = "9" ;//9
8'b1000_1000 : seg_monitor = "A" ;//A
8'b1000_0011 : seg_monitor = "b" ;//b
8'b1100_0110 : seg_monitor = "C" ;//C
8'b1010_0001 : seg_monitor = "d" ;//d
8'b1000_0110 : seg_monitor = "E" ;//E
8'b1000_1110 : seg_monitor = "F" ;//F
default    : seg_monitor = "X" ;//null
endcase
end

endmodule
最后是dds_controller
module dds_controller(
input wire clk,
input wire rst_n,
input wire key_out,
input wire sine_q,
input wire    square_q,
input wire    triangle_q,
output wire addr,
output reg o_wave,
output wire data
);

parameter phase = 8'd64;//初始相位
//parameter Freq1K = 107374;// 40Mhz=VGA_clk,频率控制字1k/40Mhz*(2^32)=107374
parameter Freq500 =53687;// 40Mhz=VGA_clk,频率控制字500/40Mhz*(2^32)=53687

reg wave_cnt;//切换波形计数器
reg fren_cnt;//切换频率计数器
reg ampl_cnt;//切换振幅计数器
reg addr_cnt;//相位累加器位数N=32
reg freq;//构造的输出目标频率
reg m_wave;//构造的中间波形
//数码管显示
assign data = {4'hA,wave_cnt,4'hB,fren_cnt,4'hC,ampl_cnt};
//相位累加
always @(posedge clk or negedge rst_n)
if(rst_n==1'b0)
begin
addr_cnt <= phase;
addr_cnt <= 24'd0;
end
else
   addr_cnt <= addr_cnt + freq;

assign addr = addr_cnt;
//切换波形wave_cnt
always @(posedge clk or negedge rst_n)
if(rst_n==1'b0)
wave_cnt <= 4'd0;
else if(key_out==1'b0)
wave_cnt <= wave_cnt;
else if(wave_cnt<4'd2)
wave_cnt <= wave_cnt + 4'd1;
else
wave_cnt <= 4'd0;

always @(*)
case(wave_cnt)
0 : m_wave = sine_q;
1 :m_wave = square_q;
2 : m_wave = triangle_q;
default : ;
endcase
//切换频率fren_cnt
always @(posedge clk or negedge rst_n)
if(rst_n==1'b0)
fren_cnt <= 4'd0;
else if(key_out==1'b0)
fren_cnt <= fren_cnt;
else if(fren_cnt<10)
fren_cnt <= fren_cnt + 4'd1;
else
fren_cnt <= 4'd0;

always @(*)
case(fren_cnt)
0 : freq = Freq500 *74;//37Khz
1 : freq = Freq500 *75;//37.5Khz
/*2 : freq = Freq1K *38;//38Khz
3 : freq = Freq1K *38.5;//38.5Khz
4 : freq = Freq1K *39;//39Khz
5 : freq = Freq1K *39.5;//39.5Khz
6 : freq = Freq1K *40;//40Khz
7 : freq = Freq1K *35;//35Khz
8 : freq = Freq1K *35.5;//35.5Khz
9 : freq = Freq1K *36;//36Khz
10: freq = Freq1K *36.5;//36.5Khz*/
default : ;
endcase
//切换振幅ampl_cnt
always @(posedge clk or negedge rst_n)
if(rst_n==1'b0)
ampl_cnt <= 4'd3;
else if(key_out==1'b0)
ampl_cnt <= ampl_cnt;
else if(ampl_cnt<3)
ampl_cnt <= ampl_cnt + 4'd1;
else
ampl_cnt <= 4'd0;

always @(*)
case(ampl_cnt)
0 : o_wave = (m_wave>>2) + 8'd96;//ampl*1/4,middle value=128
1 : o_wave = (m_wave>>1) + 8'd64;
2 : o_wave = (m_wave>>2) +(m_wave>>1) + 8'd32;
3 : o_wave = o_wave;
default :;
endcase

endmodule

lcytms 发表于 2018-11-20 23:18:59

yangjie1993 发表于 2018-11-20 22:11
老师，看过您在腾讯课堂的课，现在遇到一些问题，请问可以帮忙看看问题在哪嘛？谢谢见帖子
请问我这个o_w ...

用仿真来查找问题，o_wave的前一级是m_wave，往前查，看问题究竟出在哪里。
故障定位了，解决问题就好办了。
另外最后面的3： o_wave = o_wave不对，应该是3： o_wave = m_wave。
可以加我微信lcytms详谈。

页: [1] 2

fpga论坛|fpga设计论坛's Archiver

北理工选修课第十四课 VGA（DDS波形显示）