整体性能分析
整体性能分析整体综合仿真的报告如下:
Device utilization summary:
Selected Device: 2s100epq208-6
Number of Slices: 710out of 1200 59%
Number of Slice Flip Flops: 648out of 2400 27%
Number of 4 input LUTs: 1096out of 2400 45%
Number of bonded IOBs: 20 out of 146 13%
Number of TBUFs: 24 out of 1200 2%
Number of BRAMs: 8 out of 10 80%
Number of GCLKs: 1 out of 425%
Timing Summary:
Speed Grade:-6
Minimum period: 12.911ns (Maximum Frequency: 77.453MHz)
Minimum input arrival time before clock: 21.516ns
Maximum output required time after clock: 6.986ns
Maximum combinational path delay: No path found
整个系统可以达到的最高频率为77. 453MHz，因此，在实验板上的50MHz时钟频率下
能正常工作。
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