Altera推荐的寄存器的写法

Verilog Register with High Power-Up Value

reg q = 1’b1; //q has a default value of ‘1’
always @ (posedge clk)
begin
q <= d;
end

直接不需要复位端口，在定义变量时直接赋值

VHDL Register with High Power-Up Level
SIGNAL q : STD_LOGIC := '1'; -- q has a default value of '1'
PROCESS (clk, reset)
BEGIN
IF (rising_edge(clk)) THEN
q <= d;
END IF;
END PROCESS;

Altera推荐的寄存器的写法

Altera推荐的寄存器的写法

Altera推荐的寄存器的写法