安德鲁上海招聘 Senior FPGA/ASIC Designer

Senior FPGA/ASIC Designer Job Description:

The ideal candidate will have extensive experience writing complex VHDL for large FPGA or ASIC designs and will be familiar with ASIC design flow.  This includes using version control to track code changes, using a bit exact model to verify rtl functionality, excellent communications skills and good documentation practices.  The candidate must be able to complete complex design assignments with minimal supervision.

Senior FPGA/ASIC Designer Job Requirements:


•        VHDL experience is required.  VHDL experience must include both RTL and behavioral level coding with significant experience writing code related to communications and signal processing functions.   Experience writing VHDL to implement DSP and processor interfaces as well as communications interfaces such as CPRI or OBSAI is highly desired.  Experience should also include the ability to write system level testbenches.

•        Experience designing complex systems with Altera Stratix-III,IV,V or Arria II Gx FPGAs or Xilinx Virtex 5, Virtex 6  FPGAs including familiarity with Altera’s Quartus design tool or Xilinx’s ISE tools.  ASIC and/or Altera Hardcopy design experience is highly desired.

•        Experience using MATLAB & Simulink for system level verification is required.

•        Experience with Mentor’s Modelsim simulator is required

•        Digital board level design experience as well as the ability to write scripts in Perl and TCL is highly desired.


B.S.E.E. required.  M.S.E.E preferred.  A minimum of 5 years work experience designing and simulating FPGAs/ASICs is required.

安德鲁科技(上海)有限公司(康普旗下公司)
上海市漕河泾开发区桂平路410号兴园大厦1楼
有意者请发送简历至：ezhang@commscope.com