FPGA生产产商提供了IP, 如何用第三方软件, 如Advantage 或 ACTIVE vhdl, 调用并进行仿真?
答:The IPs provided by Xilinx, e. g. PCI, come with simulation models which can be processed by 3rd part simulation tools like Modelsim. So there is no problem for functional simulation. Timing simulation can be done by exporting the post-layout vhdl/verilog model from Xilinx ISE software. In some cases, sample testbenches are also included. (参考译文:Xilinx提供的IP, 例如PCI, 是与仿真模型一同提供的, 这种模型可由第三方仿真工具, 如Modelsim来处理. 因此对功能仿真来说, 没有问题. 通过从Xilinx ISE软件中导出post-layout vhdl/verilog可以执行定时仿真. 在某些情况下, 也包括样本测试平台. ) |