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verilog运算符及表达式

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fpga_feixiang 发表于 2019-10-21 10:34:51 | 显示全部楼层 |阅读模式
基本运算符:+ - * / %
        位运算符:~ & | ^ ^~
        逻辑运算符:&& || !
&#160; &#160; &#160; &#160; 关系运算符:< > <= >=
&#160; &#160; &#160; &#160; 等式运算符:== != (不管x、z,结果可能是不定值)
&#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; &#160; === !==(对参数的x、z都进行比较)
&#160; &#160; &#160; &#160; 移位运算符:<< >>
&#160; &#160; &#160; &#160; 位拼接运算符:{ },将几个信号拼接起来,例如{a,b[3:0],w,3'b100}
&#160; &#160; &#160; &#160; 缩减运算符:C =&B;C =|B;C =^B;
&#160; &#160; &#160; &#160; 优先级别:和c语言差不多,加括号
&#160; &#160; 赋值语句:
&#160; &#160; &#160; &#160; 1)非阻塞赋值方式(b <= a)
&#160; &#160; &#160; &#160; &#160; &#160; a.块结束才完成赋值
&#160; &#160; &#160; &#160; &#160; &#160; b.b的值不是立刻就改变的
&#160; &#160; &#160; &#160; &#160; &#160; c.在可综合的模块中常用
&#160; &#160; &#160; &#160; 2)阻塞赋值方式(b = a)
&#160; &#160; &#160; &#160; &#160; &#160; a.赋值语句执行完成后,块才结束
&#160; &#160; &#160; &#160; &#160; &#160; b.b的值在赋值语句执行后立刻改变
&#160; &#160; &#160; &#160; &#160; &#160; c.可能会产生意想不到的结果
&#160; &#160; &#160; &#160; 简单理解:
&#160; &#160; &#160; &#160; &#160; &#160; 非阻塞赋值用了多个触发器,每次时钟到达,所有触发器都触发一次
&#160; &#160; &#160; &#160; &#160; &#160; 阻塞赋值连到同一个触发器上,时钟到达,导致所有寄存器被赋值
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晓灰灰 发表于 2019-10-22 12:17:28 | 显示全部楼层
verilog运算符及表达式
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