FPGA Designer 杭州依赛通信有限公司

发布日期：        2010-05-24        工作地点：        杭州        招聘人数：        若干
职位描述
Major Responsibilities:

Contributor to the logic design team, responsible for developing FPGAs, ASICs and digital hardware for advanced communications products.

Perform the following aspects of FPGA and ASIC design: regular interaction with other engineers, requirements analysis, specification, architecture, coding, test bench design, verification, synthesis, FPGA place and route and ASIC release.

Working in a project team, work closely with software developers

Qualifications:

BSEE/CS, or equivalent;
0 - 2 years’ relevant technical experience in hardware design;
Understanding of basic digital design techniques and computer architecture;
Familiarity with high level programming languages such as VHDL, Verilog and C.
Positive can-do disposition;
Strong work ethic;
Excellent problem solving skills;
Ability to work in a team environment are required
Excellent reading and good written communication skills in English.

Preferences:

Experiences with FPGA design using VHDL with packet processing a plus
Good verbal communication skill in English a plus.



联系方式
电子邮箱：        job.ecichina@ecitele.com