请vhdl高手帮忙看见这个程序哪儿出错了

---------------------------------------曼彻斯特编码，8位并行输入，输出为串行----------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

entity me is
port (rst,clk16x,wrn : in std_logic ;---------------wrn初始有效应该为‘1’
        din : in std_logic_vector (7 downto 0) ;
        tbre : out std_logic ; ------- 在数据发送过程中用输出信号tbre、tsre作为标志信号，当一帧数据由发送缓冲器tbr[7..0]送到发送移位寄存器tsr[7..0]时，tbre信号为1，而数据由发送移位寄存器tsr[7..0]串行发送完毕时，tsre信号为1，通知CPU在下个时钟装入新数据。
        mdo : out std_logic
) ;
end me ;

architecture v1 of me is

signal clk1x : std_logic ; --- clk1x应该是clk16x的16倍频
signal clk1x_enable : std_logic ; ---时钟使能
signal clkdiv : std_logic_vector (3 downto 0) ;-------分频时的计数信号
signal tsr : std_logic_vector (7 downto 0) ;------------ 发送移位寄存器tsr[7..0]
signal tbr : std_logic_vector (7 downto 0) ; ------------发送缓冲器tbr[7..0]
signal no_bits_sent : std_logic_vector (3 downto 0) ; -----------发送字符长度和发送次序计数器no_bits_sent
signal wrn1 : std_logic ; -----写锁存
signal wrn2 : std_logic ;
signal clk1x_disable : std_logic ; ----禁止,失去资格


begin

-- Form two bit register for write pulse-----生成一个2位寄存器 write pulse写入脉冲
process (rst,clk16x,wrn,wrn1,wrn2) --对wrn进行脉宽处理，以防接收数据错误
begin
if rst = '1' then------------------rst为0时有效
wrn2 <= '1' ; -----?应该为0，0
wrn1 <= '1' ;-----?应该为0，0
elsif clk16x'event and clk16x = '1' then-----------(wrn1,wrn2)为(,1)时开始
wrn2 <= wrn1 ;
wrn1 <= wrn ;-----------wrn初始有效值应为‘1’
end if ;
end process ;

-- Enable clock when detect edge on write pulse当检测到写脉冲边沿时触发时钟有效

process (rst,clk16x,wrn1,wrn2,no_bits_sent) --对clk1x_enable进行控制
begin
if rst = '1' or std_logic_vector(no_bits_sent) = "1010" then
clk1x_enable <=  '0' ;
elsif clk16x'event and clk16x = '1' then
if (wrn1 = '1' and wrn2 = '0')  then
clk1x_enable <= '1' ;
elsif std_logic_vector(no_bits_sent) = "1001" then
clk1x_enable <= '0' ;
end if ;
end if ;
end process ;
-- Generate Transmit Buffer Register Empty signal产生发送缓冲寄存器空闲信号

process (rst,clk16x,wrn1,wrn2,no_bits_sent)
begin
if rst = '1' then
tbre <= '1' ;---------------------此时无效
elsif clk16x'event and clk16x = '1' then
if (wrn1 = '1' and wrn2 = '0')  then
tbre <= '0' ;
elsif (std_logic_vector(no_bits_sent) = "0010") then----“1010”
tbre <= '1' ;
else
tbre <= '0' ;
end if ;
end if ;
end process ;

-- Detect edge on write pulse to load transmit buffer检测写入脉冲边沿以装载传输缓冲区

process (rst,clk16x,wrn1,wrn2) ---接收数据至tbr(发送缓冲器)
begin
if rst = '1' then
tbr <= "00000000" ;------初始数据全部写零
elsif clk16x'event and clk16x = '0' then
if wrn1 = '1' and wrn2 = '0' then
tbr <= din ;-----------满足条件时写入输入的数据
end if ;
end if ;
end process ;

-- Increment clock 倍频

process (rst,clk16x,clkdiv,clk1x_enable) --产生发送字符长度和发送次序计数器
begin
if rst = '1' then
clkdiv <= "0000" ;
elsif clk16x'event and clk16x = '1' then
if clk1x_enable = '1' then----------------- clk1x_enable = '1有效时开始倍频？？技术
clkdiv <= clkdiv + "0001" ;----------------- clkdiv 的初始值应为多少？？要不要给定
end if ;
end if ;
end process ;

clk1x <= clkdiv(3) ; --产生clk1x时钟

-- Load TSR(发送移位寄存器) from TBR(发送缓冲器), shift TSR

process (rst,clk1x,no_bits_sent,tsr)
begin
if rst = '1' then
tsr <= "00000000" ; ------初始数据全部写零
elsif clk1x'event and clk1x = '1' then
if std_logic_vector(no_bits_sent) = "0001" then
tsr <= tbr ; ----发送缓冲器tbr数据进入发送移位寄存器tsr
elsif std_logic_vector(no_bits_sent) >= "0010" and std_logic_vector(no_bits_sent) <= "1010" then
tsr <= tsr(6 downto 0)  & '0' ; --从低位到高位进行移位输出至串行输出端
else
tsr <= tsr ;
end if ;
end if ;
end process ;

-- Generate Manchester data from NRZ从不归零码中产生曼彻斯特编码

mdo <= tsr(7) xor clk1x ;

-- Calculate the number of bits sent计算发送位

process (clk1x,rst,clk1x_disable,clk1x_enable,no_bits_sent)
begin
if rst = '1' or clk1x_disable = '1' then
no_bits_sent <= "0000" ;------------没有数据发送时为“0000”
elsif clk1x'event and clk1x = '1'  then
if clk1x_enable = '1' then
no_bits_sent <= no_bits_sent + "0001" ;
end if  ;
end if  ;
end process ;

clk1x_disable <= not clk1x_enable ;

end ;
哪儿出问题了，求帮忙改正，程序上的注释是我自己写的，不知道有没有理解错