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职位类别:计算机软、硬件/互联网/IT
工作地点:北京 正在加载更多城市 发布日期:2010-06-03
工作经验:5-10年 最低学历:本科
管理经验:否 工作性质:全职
招聘人数:1人 职位月薪:1000-50000元/月
职位描述/要求:
Senior ASIC/FPGA Designer
Job description
· You will be an important person in our HW team, participate in ASIC and/or FPGA design for our in-house project, or on-site support for customer project.
· You will work with the complete ASIC/FPGA design chain including pre-study, system design, implementation, verification and maintenance.
Technical Skills
· Very good experience in VHDL/Verilog/SystemVerilog.
· Very good understanding of ASIC and/or FPGA design flow.
· Experienced in Xilinx or Altera FPGA and tools.
· Good understanding and experience of SOC design including high speed interfaces.
· Experienced in scripting like Perl, Shell or TCL
· Experienced with CM tools like Clearcase
· Experienced in one or more of the following areas is a plus:
o Wireless telecommunication standards like GSM, CDMA, WCDMA, WiMAX, TD-SCDMA or LTE
o Wired network technologies like E1, SONET/SDH, PDH, EoS, MEF, PON, IP Access Aggregation, ATM
Other qualifications:
· M.Sc. In Electrical & Electronic Engineering or similar
· At least 5 years professional experience
· Strong analytical and problem solving skills
· Self-motivated, achievement oriented and a good team player
· Good command of oral and written English & Chinese
· Can travel for 3~6 months, domestic or overseas
联系方式:
china.info@tieto.com |
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