发布日期: 2010-04-09 工作地点: 上海 招聘人数: 若干
工作年限: 三年以上 语言要求: 英语 良好 学 历: 本科
职位描述
Responsibilities:
* Be a team member to develop FPGA for communication and Storage products.
* Participate in the whole FPGA development flow, including specification, coding, simulation, physical implementation and onboard debugging.
* Communicate and cooperate cross functional teams (hardware, software, etc.) to ensure robust product development
* Candidate with hardware or test bench design experience is preferred
Prefer design experience as following implementation with FPGA:
* Xilinx Spartan/Virtex series FPGA, Altera Cyclone/Stratix series FPGA
* FIFO, RAM implementation
* High speed serial interface, including LVDS, LVPECL, CML, Rapid IO
* Timing synchronization
Skills:
* FPGA design processes including programming, constraints edit, functional verification, logic synthesis, floorplan and route, timing verification
* Hardware description language VHDL, Verilog HDL, System Verilog
* Development tools including Xilinx ISE, Altera Quartus
* Simulation tools of ModelSim SE
* Synthesis tools of Synplicity Synplify
* BS/EE with 3+ yeas or MS/EE with 2+ years of FPGA/ASIC development experience.
* Solid logic design knowledge and skills, hardware knowledge is a plus.
* Solid Verilog RTL and testbench coding skills, good coding style.
* Familiar with at least one mainstream FPGA and development platform, Xilinx/Altera/Lattice.
* Self-motivated, team oriented
* Good documentation habit
* Able to write and communicate in English
联系方式
电子邮箱: apply_shanghai@celestica.com |