verilog 高手进来帮我双向端口的仿真错误

下面的代码是一个双向引脚的模块,现在使我郁闷了好几天的是为什么仿真时
Re_from_reg和Im_from_reg的值为0时,而Re_from_Data_Bus和Im_from_Data_Bus的值为不定态呢?这不就是一个连续赋值吗?请高手指点指点,谢谢先啦
`timescale 10ns/1ns
module Bi_Dir_Data_Bus(Re_to_from_bus,
       Im_to_from_bus,
       Re_to_Data_Bus,
       Im_to_Data_Bus,
       Re_from_Data_Bus,
       Im_from_Data_Bus,
       Cs_b,
       Re_b,
       We_b);
parameter BIT_NUM=15;
inout[BIT_NUM:0] Re_to_from_bus,
     Im_to_from_bus;
input Cs_b,
  Re_b,
  We_b;
input[BIT_NUM:0]Re_to_Data_Bus,
      Im_to_Data_Bus;
output[BIT_NUM:0]Re_from_Data_Bus,
     Im_from_Data_Bus;     
reg[BIT_NUM:0] Re_to_reg,
     Im_to_reg;
reg[BIT_NUM:0]Re_from_reg,
    Im_from_reg;      
assign Re_from_Data_Bus=Re_from_reg;
assign Im_from_Data_Bus=Im_from_reg;
assign Re_to_from_bus=((Cs_b==0)&&(Re_b==0)&&(We_b==1))?16'bzzzz_zzzz_zzzz_zzzz:Re_to_reg;
assign Im_to_from_bus=((Cs_b==0)&&(Re_b==0)&&(We_b==1))?16'bzzzz_zzzz_zzzz_zzzz:Im_to_reg;
always@(Cs_b or We_b or Re_b or Re_to_Data_Bus or Im_to_Data_Bus or Re_to_from_bus or Im_to_from_bus)
if((Cs_b==0)&&(We_b==1)&&(Re_b==0))
begin
   Re_from_reg=Re_to_from_bus;
   Im_from_reg=Im_to_from_bus;
end
else
begin
   Re_to_reg=Re_to_Data_Bus;
   Im_to_reg=Im_to_Data_Bus;
end
endmodule

加上时钟信号采用同步方式试试看。<br>
<br>
下面是用工具综合该模块时给出的警告信息：<br>
<br>
@W: CL118: ttt.v(30): Latch generated from always block for signal Re_to_reg[15:0], probably caused by a missing assignment in an if or case stmt @W:"e:\modeltech_6.1f\examples\ttt.v":30:2:30:4<br>
@W: CL118: ttt.v(30): Latch generated from always block for signal Im_to_reg[15:0], probably caused by a missing assignment in an if or case stmt @W:"e:\modeltech_6.1f\examples\ttt.v":30:2:30:4<br>
@W: CL118: ttt.v(30): Latch generated from always block for signal Re_from_reg[15:0], probably caused by a missing assignment in an if or case stmt @W:"e:\modeltech_6.1f\examples\ttt.v":30:2:30:4<br>
@W: CL118: ttt.v(30): Latch generated from always block for signal Im_from_reg[15:0], probably caused by a missing assignment in an if or case stmt @W:"e:\modeltech_6.1f\examples\ttt.v":30:2:30:4<br>
<br>
4 Verilog Compiler warnings<br>
<br>
@W: ttt.v(27): Net Re_to_from_bus_1_0 appears to be a clock source which was not identified. Assuming default frequency.&nbsp;&nbsp;@W:"e:\modeltech_6.1f\examples\ttt.v":27:24:27:54<br>
@W: ttt.v(27): Net Re_to_from_bus_1_1 appears to be a clock source which was not identified. Assuming default frequency.&nbsp;&nbsp;@W:"e:\modeltech_6.1f\examples\ttt.v":27:24:27:54<br>
@W: ttt.v(27): Net Re_to_from_bus_1_2 appears to be a clock source which was not identified. Assuming default frequency.&nbsp;&nbsp;@W:"e:\modeltech_6.1f\examples\ttt.v":27:24:27:54<br>
@W: ttt.v(27): Net Re_to_from_bus_1_3 appears to be a clock source which was not identified. Assuming default frequency.&nbsp;&nbsp;@W:"e:\modeltech_6.1f\examples\ttt.v":27:24:27:54<br>
@W: ttt.v(27): Net Re_to_from_bus_1_4 appears to be a clock source which was not identified. Assuming default frequency.&nbsp;&nbsp;@W:"e:\modeltech_6.1f\examples\ttt.v":27:24:27:54<br>
@W: ttt.v(27): Net Re_to_from_bus_1 appears to be a clock source which was not identified. Assuming default frequency.&nbsp;&nbsp;@W:"e:\modeltech_6.1f\examples\ttt.v":27:24:27:54<br>
<br>
6 Mapper warnings

大家一起看看

楼主想实现什么呢？<br>
<br>
端口和变量的名字都取得太相近了，也没有说明，绕来绕去有点看不明白楼主的意愿。

n,,nnnnnnn

楼主怎么取这样的名字，看得人眼花缭乱。

哈哈,看不动的说