串并转换用一个任务实现,然后在通过在always里调用任务;如把一串数据转换位一个8位并行数据输出:注意代码如下<br>
...<br>
reg serial; //存储串行数据的寄存器<br>
reg [7:0] parallel; //并行数据的输出寄存器<br>
reg [8:0] shift_state; //状态机变量<br>
parameter shift_bit7 = 9'b000000001,<br>
shift_bit6 = 9'b000000010,<br>
shift_bit5 = 9'b000000100,<br>
shift_bit4 = 9'b000001000, <br>
shift_bit3 = 9'b000010000, <br>
shift_bit2 = 9'b000100000,<br>
shift_bit1 = 9'b001000000,<br>
shift_bit0 = 9'b010000000,<br>
shift_end = 9'b100000000;<br>
<br>
always @ (posedge clk)<br>
begin<br>
shift_state <= shift_bit7; //初始化移位状态变量,使其有一个初状态<br>
if(...) <br>
shift; //在条件成立的时候调用任务 <br>
end<br>
<br>
//定义串并移位的任务<br>
task shift;<br>
begin<br>
case(shift_state)<br>
shift_bit7: begin <br>
parallel[7] <= serial;<br>
shift_state <= shift_bit6; <br>
end<br>
shift_bit6: begin <br>
parallel[6] <= serial;<br>
shift_state <= shift_bit5; <br>
end<br>
shift_bit5: begin <br>
parallel[5] <= serial;<br>
shift_state <= shift_bit4; <br>
end<br>
shift_bit4: begin <br>
parallel[4] <= serial;<br>
shift_state <= shift_bit3; <br>
end<br>
shift_bit3: begin <br>
parallel[3] <= serial;<br>
shift_state <= shift_bit2; <br>
end<br>
shift_bit2: begin <br>
parallel[2] <= serial;<br>
shift_state <= shift_bit1; <br>
end<br>
shift_bit1: begin <br>
parallel[1] <= serial;<br>
shift_state <= shift_bit0; <br>
end<br>
shift_bit0: begin <br>
parallel[0] <= serial;<br>
shift_state <= shift_end; <br>
end<br>
shift_end: shift_state <= shift_end;<br>
default:shift_state <= shift_end;<br>
endcase<br>
end<br>
endtask |