verilog请教程序中的一点小问题

`timescale 1ns/100ps
module div_freq (
     reset_n,
     clockin,
     datain,
     clockout
      );
input     reset_n;
input     clockin;
input[7:0]  datain;
output    clockout;
reg     clockout;
reg  [7:0]  counter;

always @( posedge clockin or negedge reset_n ) begin
  if ( ~reset_n ) begin
   counter <= 8'h00;
  end
  else if ( ~|counter ) begin
   counter <= datain;
  end
  else begin
   counter <= counter - 8'h01;
  end
end
//
// If we use the carry out as clock out, duty cycle is not 50%.
//
// wire cout;
// assign cout = (counter == 8'hff);
//
//
// If we use the following clockout as clock out, duty cycle is 50%.
// However, we must know the following code has included 2-div
// frequence.
//
always @( posedge clockin or negedge reset_n ) begin
  if ( ~reset_n ) begin
   clockout <= 1'b0;
  end
  else if ( ~|counter ) begin
   clockout <= ~clockout;
  end
end
endmodule
请问粗体字中的~|counter是什么意思

咋的没人来帮忙呢????????????????????

是归约运算符或非<br>
&bull; | ( 归约或)<br>
如果存在位值为1，那么结果为1；如果存在位x或z，结果为x；否则结果为0。<br>
&bull; ~| ( 归约或非)<br>
与归约操作符|相反。

谢谢楼上 小弟刚学几天 呵呵

一起学习，一起进步

共同学习,不过这个还是用的比较少

恩，不怎么常见，我在考试复习时看过，