8位全加器的例子？

这是一个教程给出的例子，怎么运行不了，仿真不出来
8位全加器
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY adder8 IS

PORT (a, b
: IN
std_LOGIC_vector(6 DOWNTO 0);

Ci
: IN
bit;


result
: OUT std_LOGIC_vector(7 DOWNTO 0) ）;
END adder8;
ARCHITECTURE behave OF adder8 IS
signal halfadd
: std_LOGIC_vector(7 DOWNTO 0);
BEGIN

halfadd <=a + b;

result <= halfadd WHEN ci=’0’ ELSE halfadd+1;
END behave;

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8  位为什么还是(6 DOWNTO