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我觉得应该这样写：
`timescale 1ns / 1ps
module serial2pal(
//input
clk, //clock signal
reset, //reset signal
enable, //enable signal
data_in, //serial data in
data_head, //head of the useful data, used for head check
data_tail, //tail of the useful data, used for tail check
//output
odd_bits, //indicate the result of odd and even check
even_bits,
data_out,
check_head, //add
check_tail, //add
seta //add
);
//clock and reset signal description
input clk;
input reset;
//input signal description
input enable;
input data_in;
input [7:0] data_head;
input [7:0] data_tail;
//output description
output odd_bits;
output even_bits;
output [7:0] data_out;
output [7:0] check_head; //add
output [7:0] check_tail; //add
output seta; //add
reg [3:0] n;
reg [7:0] data_out;
parameter temp_head=8'b11111111; //add
parameter temp_tail=8'b00000000; //add
//internal signal description
reg seta; //used to indicate whether we have got the data header.
reg [7:0] check_head; //used to check the data_head
reg [7:0] check_tail; //used to check the end of the useful data
always@(posedge clk or negedge reset)
begin
if(!reset)
begin
seta<=0;
check_head<=0;
check_tail<=0;
end
else
begin
check_head={check_head[6:0],data_in};
check_tail={check_tail[6:0],data_in};
if(check_head==temp_head)
seta<=1;
else if(check_tail==temp_tail)
seta<=0;
end
end
always@(posedge clk or negedge reset)
begin
if(!reset)
data_out<=0;
else
begin
if(n<=7)
begin //
if(seta==1)
begin
data_out<={data_out[6:0],data_in};
n=n+1;
end
else
n=0;
end
else
begin
n=0;
data_out=8'bx;
end
end
end
//assign odd_bits=^data_out;
//assign even_bits=~odd_bits;
endmodule |
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