我写了一个矩阵转化的代码,可综合时老是报错.哪为高手帮看看错在哪里,怎么改?
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity matrix8_32 is
port(yin:in std_logic_vector(31 downto 0);
d: in std_logic_vector(7 downto0);
yout:in std_logic_vector(7 downto 0);
q: out std_logic_vector(31 downto 0)
);
end entity;
architecture rtl of matrix8_32 is
signal data0,data1,data2,data3,data4,data5,data6,data7 :std_logic_vector(7 downto 0);
signal data8, data9,data10,data11,data12,data13,data14,data15 :std_logic_vector(7 downto 0);
signal data16,data17,data18,data19,data20,data21,data22,data23:std_logic_vector(7 downto 0);
signal data24,data25,data26,data27,data28,data29,data30,data31:std_logic_vector(7 downto 0);
begin
process(yin,d,yout)
begin
if yin(0)'event and ( yin(0) = '1')then
data0<=d;
elsif yin(1)'event and (yin(1)='1')then
data1<=d;
elsif yin(2)'event and (yin(2)='1')then
data2<=d;
elsif yin(3)'event and (yin(3)='1')then
data3<=d;
elsif yin(4)'event and (yin(4)='1')then
data4<=d;
elsif yin(5)'event and (yin(5)='1')then
data5<=d;
elsif yin(6)'event and (yin(6)='1')then
data6<=d;
elsif yin(7)'event and (yin(7)='1')then
data7<=d;
elsif yin(8)'event and (yin(8)='1')then
data8<=d;
elsif yin(9)'event and (yin(9)='1')then
data9<=d;
elsif yin(10)'event and (yin(10)='1')then
data10<=d;
elsif yin(11)'event and (yin(11)='1')then
data11<=d;
elsif yin(12)'event and (yin(12)='1')then
data12<=d;
elsif yin(13)'event and (yin(13)='1')then
data13<=d;
elsif yin(14)'event and (yin(14)='1')then
data14<=d;
elsif yin(15)'event and (yin(15)='1')then
data15<=d;
elsif yin(16)'event and (yin(16)='1')then
data16<=d;
elsif yin(17)'event and (yin(17)='1')then
data17<=d;
elsif yin(18)'event and (yin(18)='1')then
data18<=d;
elsif yin(19)'event and (yin(19)='1')then
data19<=d;
elsif yin(20)'event and (yin(20)='1')then
data20<=d;
elsif yin(21)'event and (yin(21)='1')then
data21<=d;
elsif yin(22)'event and (yin(22)='1') then
data22<=d;
elsif yin(23)'event and (yin(23)='1') then
data23<=d;
elsif yin(24)'event and (yin(24)='1') then
data24<=d;
elsif yin(25)'event and (yin(25)='1') then
data25<=d;
elsif yin(26)'event and (yin(26)='1') then
data26<=d;
elsif yin(27)'event and (yin(27)='1') then
data27<=d;
elsif yin(28)'event and (yin(28)='1') then
data28<=d;
elsif yin(29)'event and (yin(29)='1') then
data29<=d;
elsif yin(30)'event and (yin(30)='1') then
data30<=d;
elsif yin(31)'event and (yin(31)='1') then
data31<=d;
else null;
end if;
case yout is
when "11111110" =>q<=(data31(7)&data30(7)&data29(7)&data28(7)&data27(7)&data26(7)&data25(7)&data24(7)&data23(7)&data22(7)&data21(7)&data20(7)&data19(7)&data18(7)&data17(7)&data16(7)&data15(7)&data14(7)&data13(7)&data12(7)&data11(7)&data10(7)&data9(7)&data8(7)&data7(7)&data6(7)&data5(7)&data4(7)&data3(7)&data2(7)&data1(7)&data0(7));
when "11111101" =>q<=(data31(6)&data30(6)&data29(6)&data28(6)&data27(6)&data26(6)&data25(6)&data24(6)&data23(6)&data22(6)&data21(6)&data20(6)&data19(6)&data18(6)&data17(6)&data16(6)&data15(6)&data14(6)&data13(6)&data12(6)&data11(6)&data10(6)&data9(6)&data8(6)&data7(6)&data6(6)&data5(6)&data4(6)&data3(6)&data2(6)&data1(6)&data0(6));
when "11111011" =>q<=(data31(5)&data30(5)&data29(5)&data28(5)&data27(5)&data26(5)&data25(5)&data24(5)&data23(5)&data22(5)&data21(5)&data20(5)&data19(5)&data18(5)&data17(5)&data16(5)&data15(5)&data14(5)&data13(5)&data12(5)&data11(5)&data10(5)&data9(5)&data8(5)&data7(5)&data6(5)&data5(5)&data4(5)&data3(5)&data2(5)&data1(5)&data0(5));
when "11110111" =>q<=(data31(4)&data30(4)&data29(4)&data28(4)&data27(4)&data26(4)&data25(4)&data24(4)&data23(4)&data22(4)&data21(4)&data20(4)&data19(4)&data18(4)&data17(4)&data16(4)&data15(4)&data14(4)&data13(4)&data12(4)&data11(4)&data10(4)&data9(4)&data8(4)&data7(4)&data6(4)&data5(4)&data4(4)&data3(4)&data2(4)&data1(4)&data0(4));
when "11101111" =>q<=(data31(3)&data30(3)&data29(3)&data28(3)&data27(3)&data26(3)&data25(3)&data24(3)&data23(3)&data22(3)&data21(3)&data20(3)&data19(3)&data18(3)&data17(3)&data16(3)&data15(3)&data14(3)&data13(3)&data12(3)&data11(3)&data10(3)&data9(3)&data8(3)&data7(3)&data6(3)&data5(3)&data4(3)&data3(3)&data2(3)&data1(3)&data0(3));
when "11011111" =>q<=(data31(2)&data30(2)&data29(2)&data28(2)&data27(2)&data26(2)&data25(2)&data24(2)&data23(2)&data22(2)&data21(2)&data20(2)&data19(2)&data18(2)&data17(2)&data16(2)&data15(2)&data14(2)&data13(2)&data12(2)&data11(2)&data10(2)&data9(2)&data8(2)&data7(2)&data6(2)&data5(2)&data4(2)&data3(2)&data2(2)&data1(2)&data0(2));
when "10111111" =>q<=(data31(1)&data30(1)&data29(1)&data28(1)&data27(1)&data26(1)&data25(1)&data24(1)&data23(1)&data22(1)&data21(1)&data20(1)&data19(1)&data18(1)&data17(1)&data16(1)&data15(1)&data14(1)&data13(1)&data12(1)&data11(1)&data10(1)&data9(1)&data8(1)&data7(1)&data6(1)&data5(1)&data4(1)&data3(1)&data2(1)&data1(1)&data0(1));
when "01111111" =>q<=(data31(0)&data30(0)&data29(0)&data28(0)&data27(0)&data26(0)&data25(0)&data24(0)&data23(0)&data22(0)&data21(0)&data20(0)&data19(0)&data18(0)&data17(0)&data16(0)&data15(0)&data14(0)&data13(0)&data12(0)&data11(0)&data10(0)&data9(0)&data8(0)&data7(0)&data6(0)&data5(0)&data4(0)&data3(0)&data2(0)&data1(0)&data0(0));
when others =>null;
end case;
end process;
end architecture;
报的错误主要如下:
Error (10820): Netlist error at Vhdl1.vhd(22): can't infer register for data31[0] because its behavior depends on the edges of multiple distinct clocks
Error (10818): Netlist error at Vhdl1.vhd(22): can't infer register for data31[0] because it does not hold its value outside the clock edge
Error (10820): Netlist error at Vhdl1.vhd(22): can't infer register for data30[1] because its behavior depends on the edges of multiple distinct clocks
哪位高手帮看一下,谢谢了 |
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