你的state定义也不对,它至少要两位才够。这是我改完并通过编译的程序:<br>
<br>
module ludeng(clk,rst,min1,min5,min10,reg_ind,major_red,major_green,minor_red,minor_green);<br>
parameter major_0=0,major_1=1,minor=2;<br>
input clk,rst,reg_ind;<br>
output min1,min5,min10;<br>
output major_red,major_green,minor_red,minor_green;<br>
reg min1,min5,min10;<br>
reg next_state,clr;<br>
reg reg_ind1;<br>
reg[1:0] state;<br>
reg cnt,major_red,major_green,minor_red,minor_green;<br>
<br>
assign reg_ind=reg_ind1;<br>
<br>
always@(posedge clk or posedge rst)<br>
begin <br>
if(rst==1'b1)<br>
state<=major_0;<br>
else state<=next_state;<br>
end<br>
<br>
always@(state or min1 or min5 or min10 or reg_ind)<br>
begin <br>
case(state)<br>
major_0:<br>
begin<br>
major_green=1'b1;<br>
minor_red=1'b1;<br>
if(min5==1'b1)<br>
next_state=major_1;<br>
else next_state<=major_0;<br>
end<br>
major_1:<br>
begin<br>
if((min10==1'b1)||(reg_ind==1'b1))<br>
next_state=minor;<br>
else next_state=major_1;<br>
end<br>
minor:<br>
begin<br>
minor_green=1'b1;<br>
major_red=1'b1;<br>
if(min1==1'b1)<br>
next_state=major_0;<br>
else next_state=minor;<br>
end<br>
default:<br>
next_state=major_0;<br>
endcase<br>
end<br>
<br>
always@(posedge clk)<br>
begin <br>
if(rst==1'b1)<br>
cnt=10'h000;<br>
else <br>
if(clr==1'b1)<br>
cnt=10'h000;<br>
else cnt=cnt+1'b1;<br>
end<br>
<br>
always@(cnt or state)<br>
begin <br>
if((state=major_0)&&(cnt==9'd299))<br>
min5=1'b1;<br>
else min5=1'b0;<br>
end<br>
<br>
always@(cnt or state)<br>
begin <br>
if((state=major_1)&&(cnt==9'd299))<br>
min10=1'b1;<br>
else min10=1'b0;<br>
end<br>
<br>
always@(min1 or min5 or min10)<br>
begin <br>
if(min1||min5||min10)<br>
clr=1;<br>
else clr=0;<br>
end<br>
<br>
always@(rst or state)<br>
begin<br>
if(rst==1)<br>
reg_ind1<=1'b0;<br>
else <br>
if(state==minor)<br>
reg_ind1<=1'b0;<br>
end<br>
<br>
endmodule |