FPGA应用工程师FPGA Application Engineer 雅格罗技（北京）科技有限公司

发布日期：        2010-07-02        工作地点：        北京-海淀区        招聘人数：        若干
工作年限：        二年以上        语言要求：        英语 良好        学    历：        本科
职位描述
Job Responsibilities:
Responsible for providing support for customers logic and/or system design. Support in-depth technical inquiries, providing design evaluations and recommendations, and creating technical collaterals including documentation, design examples and demos. Work with the development teams to provide feedback to improve Agate’s design tools and methodology. Seniority depends on levels of experience.
Requirements:
- BSEE or equivalent with 2+ years, or a MSEE with 1+ years of relevant project experience.
- At least 1 to 2 years of FPGA design experience.
- Familiar with the software and hardware design using MCU products.
- Familiar with Verilog HDL and/or VHDL.
- Familiar with assembly language and/or C language.
- Capable of working in a team and skillful in communication
Preferences:
- System level experience with FPGA architectures, microprocessors, memory controllers, DSP, networking, storage, and communications.
- Skillful in high-speed board level system design.
- Familiarity with Synopsys Design Compiler and Synplicity.
- Skillful in C++, shell scripts, Python, and/or Perl.
职位描述:
为更深层次的技术需求提供解决方案，提供设计评估和建议。建立和维护技术资料库，包括技术文档，设计流程及实例。协助开发团队优化并完善公司产品及方案。
职位要求：
-BSEE，具有2年以上工作经验；或者MSEE, 一年以上相关项目经验
-至少1到2年FPGA设计经验
-熟悉MCU 产品的硬软件设计
-熟悉Verilog HDL / VHDL语言
-熟悉汇编/C语言
-良好的团队合作精神和交流能力
-有FPGA系统级构架经验，及熟悉微处理器，存储控制，DSP等相关知识者优先
-熟悉高速板级系统设计者优先
-熟悉Synopsys Design Compiler和 Synplicity者优先
-熟悉C++, shell scripts, Python, and/or Perl者优先
Email: hr@agatelogic.com.cn