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本帖最后由 fpgaw 于 2010-11-12 06:29 编辑
我用的芯片是:EP1C3T144C8,做了一个PLL,输入频率:100MHZ,输出:50MHZ和100MHZ,但是波形仿真不了,即输出高阻态
出现这样的警告:Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled
Warning: Output port clk0 of PLL "cyc_pll:inst1|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
请教是怎么回事?谢谢! |
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