architecture bahav of trans is
signal s1,s2,s3:std_logic_vector(7 downto 0);
begin
process(s1,C,A,S)
begin
if S="00" then
s1 <= C;
else s1 <="ZZZZZZZZ";
end if;
A<=s1;
end process;
process(s2,C,A,S)
begin
if S="01" then
s2 <= A;
else s2 <="ZZZZZZZZ";
end if;
C<=s2;
end process;
process(s3,C,B,S)
begin
if S="10" or S="11" then
s3 <= B;
else s3<="ZZZZZZZZ";
end if;
C<=s3;
end process;
end bahav;
怎么理解其中的一个Process,