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module lcd(clk,reset,rs,rw,en,dat);
input clk,reset;//
output rs,rw,en;
output[7:0] dat;
reg rs,rw;
wire en;
reg[7:0] dat;
reg[7:0] dats;
reg[3:0] state;
reg[3:0] count_cnt;
reg[5:0] counter;
reg[5:0] address;
reg[19:0] div_cnt;
wire cnt;
reg flag;
reg clkr;
reg tc_clk;
parameter
init=4'b0000,
setbase1=4'b0001,
setbase2=4'b0010,
setmode1=4'b0011,
setmode2=4'b0100,
moveleft=4'b0101,
setddram=4'b0110,
writeram=4'b0111;
assign en=clkr;
assign cnt=(div_cnt==20'h8ffff);
always @(posedge clk or negedge reset)
begin
if(!reset)
div_cnt=20'd0;
else
div_cnt=div_cnt+1'b1;
end
always @(posedge clk or negedge reset)
begin
if(!reset)
tc_clk<=0;
else if(cnt)
tc_clk=~tc_clk;
end
always @(posedge tc_clk or negedge reset)
begin
if(!reset)
clkr<=0;
else
clkr=~clkr;
end
always @(posedge clkr or negedge reset)
begin
if(!reset)
begin
count_cnt<=0;
counter<=0;
state<=init;
flag<=0;
end
else
begin
case(state)
init:
if(flag==0)
begin
state<=setbase1;
counter<=0;
count_cnt<=0;
flag<=1'b1;
end
else
if(count_cnt<='b1100)
begin
count_cnt<=count_cnt+1'b1;
state<=init;
end
else
begin
state<=moveleft;
count_cnt<=0;
end
setbase1:state<=setbase2;
setbase2:state<=setmode1;
setmode1:state<=setmode2;
setmode2:state<=writeram;
moveleft:state<=init;
setddram:state<=writeram;
writeram:
begin
if(counter<='d10)
begin
state<=writeram;
counter<=counter+1'b1;
end
else
if(counter<='d25)
begin
if(counter==11)
begin
state<=setddram;
counter<=counter+1'b1;
end
else
begin
state<=writeram;
counter<=counter+1'b1;
end
end
else
state<=moveleft;
end
default:state<=init;
endcase
end
end
always @(counter)
begin
case(counter)
6'b00_0000:dats<="M";
6'b00_0001:dats<="e";
6'b00_0010:dats<="n";
6'b00_0011:dats<="g";
6'b00_0100:dats<=" ";
6'b00_0101:dats<="m";
6'b00_0110:dats<="e";
6'b00_0111:dats<="n";
6'b00_1000:dats<="g";
6'b00_1001:dats<=" ";
6'b00_1010:dats<=1110_0001;
6'b00_1011:dats<=1110_0001;
6'b00_1100:dats<="F";
6'b00_1101:dats<="o";
6'b00_1110:dats<="r";
6'b00_1111:dats<="e";
6'b01_0000:dats<="v";
6'b01_0001:dats<="e";
6'b01_0010:dats<="r";
6'b01_0011:dats<=" ";
6'b01_0100:dats<="B";
6'b01_0101:dats<="r";
6'b01_0110:dats<="o";
6'b01_0111:dats<="t";
6'b01_1000:dats<="h";
6'b01_1001:dats<="e";
6'b01_1010:dats<="r";
default: dats<=8'd32;
endcase
end
always@(posedge clkr)
begin
rs<=((state==writeram))?1:0;
rw<=1'b0;
case(state)
setbase1:dat<='h38;
setbase2:dat<='h0f;
setmode1:dat<='h01;
setmode2:dat<='h06;
//setcur1:dat<='h0f;
moveleft:dat<='h18;
setddram:
if(counter==0)
dat<=8'h80;
else dat<=8'hc0;
writeram: dat<=dats;
default:dat<=8'bzzzz_zzzz;
endcase
end
endmodule |