布局布线时出现以下错误，担心skew，不想忽略，

布局布线时出现以下错误，担心skew，不想忽略，问问各位大虾小虾有没有好的解决办法： 多谢！
ERRORlace:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
   clock site pair. The clock component <MII_RXCLK_0_BUFGP/BUFG> is placed at site <BUFGMUX_X1Y11>. The IO component
   <MII_RXCLK_0> is placed at site <AD196>.  This will not allow the use of the fast path between the IO and the Clock
   buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
   in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this
   override is highly discouraged as it may lead to very poor timing results. It is recommended that this error
   condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below.
   These examples can be used directly in the .ucf file to override this clock rule.
   < NET "MII_RXCLK_0" CLOCK_DEDICATED_ROUTE = FALSE; >

不是提示了你该怎么做了么

提示是忽略这个问题，忽略会造成skew比较大，不想忽略！

不想用，那么错误原因人家也告诉你了
那……按照错误原因去解决咯

加上那条约束就行
很可能你就发现,根本不会有时序问题,如果静态时序分析出问题再说
以我做过的项目看,不会有太大影响

好的，多谢！这个时钟pad点在Bank2, 工具将BUFGMUX布在了Bank0，导致IBUFG和BUFGMUX距离太远了，能不能利用约束强制将其布线在Bank2附近？Bank2的8全局时钟资源我全用的P, 其中有两个共用了一个BUFGMUX, 难道是这个问题？

你自己loc约束指定到近的bufgmux

似乎，通常这种问题的出现，是时钟没走专用的clock pin 导致的。

感觉，Xilinx也很讨厌
这种问题得在Map时候报，而且一次不报全
浪费时间

以前版本有个设置环境变量的方法
现在不知道有没了