MWR R&D - FPGA Design Engineer 诺基亚西门子通信技术（北京）有限公司

发布日期：        2010-04-13        工作地点：        上海        招聘人数：        若干
工作年限：        二年以上        语言要求：        英语 熟练        学    历：        本科
职位描述
MWR R&D - FPGA Design Engineer

Key Responsibilities:
- Detailed logic functionality and FPGA code design/implementation.
- Simulating the needed functionality
- Generating the test bench environment for the verification
- FPGA verification planning, validation and testing on board.
- System emulation and bring-up on FPGA prototype

Job Requirements:
- Knowledge of FPGA-Design and Formal Verification tools. Good VHDL (or Verilog) RTL experience
- Good knowledge of Altera or Xilinx FPGA is an advantage
- Block level Micro-architecture, RTL Design, Verification, Synthesis and timing.
- Excellent analysis/debugging skills and using scripting languages (e.g. HiT, TCL)

Education/Skills:
- Bachelor/Master of Science (Electrical Engineering)
- >2 years working experience in the related area
- Fluent English in both speaking and writing

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