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关于用FPGA实现TDC的文章/Papers about TDC implemented in FPGA

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羽蒙 发表于 2014-7-31 11:53:53 | 显示全部楼层 |阅读模式
A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array 2010
Altera Cyclone,使用Cyclone中特有的carry-select chain、进位选择链,采用被测信号来锁定(采样)延迟链中的时钟
A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays 2006
采用全局时钟锁锁定(采样)延迟链中的信号,使用进位链
Review of methods for time interval measurements with picosecond resolution 2004
关于FPGA TDC的总结
Field programmable gate array based time-to-digital converter with 200-ps resolution 1997
Firmware-only implementation of time-to-digital converter in field programmable gate array 2003
采用Cascade chain级联链
Interpolating time counter with 100 ps resolution on a single FPGA device 2000
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