关于ISE仿真出现的问题，请高人指教

warn:the design contains one or more registers/latches that are directly incompatible with the spartan6 architecture.the two primary causes of this is either a register or latch described with beth an asynchronous set and asynchronous reset.or a register or catch described with an asynchronous polarity

请问用IES仿真VHDL时 出现以上的警告，这样对结果会不会产生影响呢