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24． 如何在设计前期分析芯片的功耗？
计算功耗的工具: ALTERA提供的QUARTUS软件就有计算功耗的功能, 它可以根据你不同的激励项量来计算功耗; 在ALTERA 的网叶上就有专门计算功耗的运算器, 请点击相关文章 它就给出了APEXII的功耗计算方法.
25． 看过“FLEX PCI Development Board”的参考设计原理图, 它利用了条线开关选择配置方式. 既然两种配置方式管脚并没有公用, 为何需要这个跳线开关呢？
答：EPC2不会影响到用下载电缆通过JTAG口配置EPF10K30A. 使用跳线开关是在选择给10K30A下载的方式, 是通过下载电缆还是EPC2.
因为将ECP2与10K30A连接成JTAG菊花链的形式通过下载电缆下载和用EPC2对10K30A下载的连接方式是不同的, 所以要将这两者分开, 详细的连接方法应该在参考设计原理图中已经描绘的很清楚了.
26． 为了保证设计可靠性, 需要重点关注哪些方面？
答：Here are a few guidelines for reliable FPGA design（关于可靠性FPGA设计的几点建议）
① Use fully synchronous design. Asynchronous design is very sensitive to path delay and is therefore not robust. An example of asychronous circuit is the SR latch which uses combinational feedback. （使用完全同步设计. 异步设计对路径延迟非常敏感, 因此不很可靠. 异步电路的一个例子是使用组合反馈的SR闭锁. ）
② Never gate your clock signal with combinational logic. Glitches may occur on any gated clock signals, which results in false triggering of flip-flops. （绝不使用组合逻辑控制时钟信号. 因为在任何门控制时钟信号上可能产生短时脉冲干扰, 最终导致错误触发flip-flop. ）
③ Never rely on gate delay. （绝不要依靠门延迟. ）
④ Enough bypass capacitors should be placed close to the power and ground pins of FPGA. Use capacitors with good high frequency response. （FPGA的电源和接地引脚附近应该放置足够多的旁路电容器. 使用优质高频响应电容器. ）
⑤ Always use the global clock buffers on the FPGA to drive internal clock signals. These clock buffers and the associated clock distribution network have been carefully designed to minimize skew. （在FPGA上始终使用全局时钟缓冲来驱动内部时钟信号. 并且已经仔细设计了这些时钟缓冲和关联时钟配电网, 以将畸变减至最小. ）
27． You said "An example of asychronous circuit is the SR latch which uses combinational feedback". How do I learn SR latch ? What is the difference between SR latch and SRFF? （“异步电路的一个例子是使用组合反馈的SR闭锁”. 请问如何理解SR闭锁？SR闭锁与SRFF有什么区别？）
答：A latch changes states whenever the gate signal is active. A FF changes states only at clock edges. （参考译文：只要门信号是活动的, 闭锁就会更改状态. 而FF只有在时钟边沿才更改状态. ）
28． Xilinx公司的芯片在热设计方面可以提供哪些工具和资料？
答：For thermal consideration, you need to know the power consumption of your FPGA and the thermal resistivity of the device package you are using. The power consumption can be estimated by the XPower tool included in Xilinx ISE software. The thermal resistivity of the device package can be found in Xilinx databook. The junction temperature can then be calculated by the following formula（至于散热问题, 需要了解所用FPGA的功耗和正在使用的器件封装的热阻系数. Xilinx ISE软件中所包含的Xpower工具可以估计功耗. 在Xilinx数据手册中可以找到器件封装的热阻系数. 然后利用下面的公式计算接合温度. ）
P = (Tj - Ta) / THETAja 其中, P=功耗；Tj=接合温度；Ta=环境温度；THETAja = 封装的热阻系数
You can then detemine if the junction temperature falls within the acceptable region. The maximum acceptable junction temperature is different for C and I grade devices. If it is higher than the max. acceptable temperature, you may consider adding a heatsink or cooling fan. （之后确定接合温度是否在允许范围内. C和I级器件允许的最高接合温度不同. 如果温度高于允许的最高值, 可能需要增加散热片或风扇. ）
29． 如果时钟进入FPGA后经过一段组合逻辑才上时钟网络, 会存在一定的延时. 综合布线后会出现信号输入延时为负值, 意味着信号比时钟先到达触发器. 那么, 怎样通过约束文件增加输入信号的延时呢？我试过对"NET"加上"MEDDELAY"的约束, 但是没效果.
答：Gating the clock signal with combinational logic is not recommended in modern high speed digital design since it may creates glitches on the gated clock signal, which results in false triggering of flip-flops. This results in a less reliable design. A common technique to remove gated clock is to make use of the clock enable pin of the flip-flop. For example, if you have a signal clko = clki & a & b driving the clock pin of a flip-flop, you can eliminate the gated clock by feeding clki directly to the FF clock pin, and have another signal en = a & b connected to the clock enable pin of the FF. ( 参考译文：在现代高速数字设计当中, 不建议使用组合逻辑门控时钟信号, 因为这将会在选通的时钟信号上产生短时脉冲波形干扰, 导致错误触发flip-flop. 这是缺乏可靠性的设计. 移除门控时钟通常所采用的技巧是使用flip-flop的时钟使能引脚. 例如, 如果有一个信号clko = clki & a & b 正在驱动flip-flop的时钟引脚, 则可以通过直接将clki传递给FF时钟引脚, 并将另一个信号en = a & b与FF的时钟使能引脚连接, 来消除门控时钟. )
By removing the gated clock, you no longer have the problem of clock delay. Also the design is more robust. (移除门控时钟后, 就不再有时钟延迟的问题了. 而且这种设计也比较可靠. ) |
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