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DES算法的modelsim仿真
module testbench1;
reg clk, reset, des_enable, des_mode;
reg [63:0] data_i, key_i;
wire [63:0] data_o;
wire ready_o;
DES d1(clk, des_enable,
reset,
des_mode,
data_i,
key_i,
data_o,
ready_o);
initial clk = 1'b0;
initial
begin
des_mode = 1'b1;
#400 reset = 1'b0; des_enable = 1'b0;
#7 reset = 1'b1; des_enable = 1'b1; des_mode = 1'b1;
data_i =64'h3b98d2eeaeb60035;
key_i =64'h0123456789abcdef;
end
always #10 clk=~clk;
endmodule
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