初学者请教高手帮我看下程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY biaoding IS
PORT( rst,up,down: IN BIT;
      DA: OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
END biaoding;

ARCHITECTURE bEhAv OF biaoding IS
BEGIN
PROCESS(rst,up,down)
VARIABLE Q:STD_LOGIC_VECTOR(11 DOWNTO 0);
VARIABLE A:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF( rst='1' )THEN A:="0101";
ELSIF( up'EVENT AND up='1')THEN A:=A+1;
ELSIF( down'EVENT AND down='1' )THEN A:=A-1;
END IF;

case A IS
WHEN "0000"=> Q:="000000001000";
WHEN "0001"=> Q:="000110100000";
WHEN "0010"=> Q:="001100111000";
WHEN "0011"=> Q:="010011010000";
WHEN "0100"=> Q:="011001101000";
WHEN "0101"=> Q:="100000000000";
WHEN "0110"=> Q:="100110011000";
WHEN "0111"=> Q:="101100110000";
WHEN "1000"=> Q:="110011001000";
WHEN "1001"=> Q:="111001100000";
WHEN "1010"=> Q:="111111110111";
WHEN OTHERS=> NULL;
END case;
      da <= Q ;
END PROCESS;
END bEhAv;


程序编译时总是提示错误Process clocking is too complex
请帮我指出问题，谢谢。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY biaoding IS
PORT( rst,up,down: IN BIT;
      DA: OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
END biaoding;

ARCHITECTURE bEhAv OF biaoding IS
signal A:STD_LOGIC_VECTOR(3 DOWNTO 0);


BEGIN
PROCESS(rst,up,down)
VARIABLE Q:STD_LOGIC_VECTOR(11 DOWNTO 0);

BEGIN
IF( rst='1' )THEN A <= "0101";
ELSIF( up='1')THEN A <= A+1;
ELSIF( down='1' )THEN A <= A-1;
END IF;

case A IS
WHEN "0000"=> Q:="000000001000";
WHEN "0001"=> Q:="000110100000";
WHEN "0010"=> Q:="001100111000";
WHEN "0011"=> Q:="010011010000";
WHEN "0100"=> Q:="011001101000";
WHEN "0101"=> Q:="100000000000";
WHEN "0110"=> Q:="100110011000";
WHEN "0111"=> Q:="101100110000";
WHEN "1000"=> Q:="110011001000";
WHEN "1001"=> Q:="111001100000";
WHEN "1010"=> Q:="111111110111";
WHEN OTHERS=> NULL;
END case;
      da <= Q ;
END PROCESS;
END bEhAv;



这样就可以了

额。。。第一段两个clock，第二段又没有clock。。。

ELSIF( up'EVENT AND up='1')THEN A:=A+1;
ELSIF( down'EVENT AND down='1' )THEN A:=A-1；

这里两个信号都取沿（event）重复，建议将up,down信号改为一般使能输入，再引入系统时钟clk。另外，程序的其他地方还存在错误