为什么在quartus ii中没错在modelsim中却提示：Unknown identifier std_logic_vecter

LIBRARY IEEE;
USE ieee.std_logic_1164.all;
ENTITY test IS
END test;
ARCHITECTURE test OF test IS
SIGNAL clock: STD_LOGIC :='0';
SIGNAL a,b: INTEGER RANGE 0 TO 3:=0;
SIGNAL        cc: INTEGER RANGE 0 TO 1:=0;
SIGNAL aaa,bbb: STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL        ccb: STD_LOGIC;
COMPONENT adder IS
        PORT (a,b:IN STD_LOGIC_VECTOR(1 DOWNTO 0);
                        clk,cc:IN STD_LOGIC;
                        s:OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
                        cout:OUT STD_LOGIC);
END COMPONENT;
--------------------------------------
FUNCTION conv_std_logic(SIGNAL x:INTEGER)
   RETURN STD_LOGIC IS
   variable result: STD_LOGIC;
BEGIN
  IF (x=0) THEN
     result:= '0';
  ELSE
      result:= '1';
        END IF;
         
  RETURN result;
END conv_std_logic;
---------------------------------------
FUNCTION conv_std_logic_vector(SIGNAL x:INTEGER)
   RETURN STD_LOGIC_VECTOR IS
   VARIABLE result:STD_LOGIC_VECTER(1 downto 0);
  BEGIN
     IF(x=0) then
         rusult :="00";
           ELSIF(x=1)then
                   rusult :="01";
                ELSIF(x=2)then
                   rusult :="10";
                ELSe
                   rusult :="11";
                end if;
RETURN result;
END conv_std_logic_vector;
----------------------------------
BEGIN
  aaa <= conv_std_logic_vector(a);
  bbb<=conv_std_logic_vector(b);
  ccb<=conv_std_logic(cc);
u1: adder PORT MAP(aaa=>a,bbb=>b,ccb=>cc,s=>open,cout=>open);
  clock <= NOT clock  AFTER 100ns;
PROCESS (clock)
  BEGIN
    IF(clock'EVENT AND clock = '1') THEN
      IF( a< 3) THEN a<=a+1; ELSE a<=0;END IF ;
    END IF;
  END PROCESS;
PROCESS (clock,a)
  BEGIN
    IF (clock'EVENT AND clock='1') THEN
      IF (a=3) THEN
      IF( b < 3) THEN  b<=b+1; ELSE b<=0;END IF ;  
      END IF;
    END IF;
  END PROCESS;
PROCESS (clock,b)
   BEGIN
    IF(clock'EVENT AND clock = '1') THEN
      IF (b=3 AND a=0) THEN
      IF (cc=0) THEN cc<=cc+1;ELSE CC<=0; END IF;
      END IF;
    END IF;
  END PROCESS;
  
END test;

adder是一个加法器，这个程序是做一个测试。加法器的正确性。