VHDL程序改错——wait语句

PACKAGE types IS
SUBTYPE nat8 is integer RANGE 255 DOWNTO 0;
END types;

USE work.types.all;

ENTITY gcd IS
PORT(reset : IN bit; -- Global reset
clk : IN bit; -- Global clock
rst : IN boolean;
xin : IN nat8;
yin : IN nat8;
rdy : OUT boolean;
oup : OUT nat8);
END gcd;

ARCHITECTURE algorithm OF gcd IS
BEGIN
gcd: PROCESS
VARIABLE x : nat8;
VARIABLE y : nat8;
VARIABLE h : nat8;
BEGIN

rdy <= true;
oup <= 0;

RESET_LOOP : LOOP

WAIT UNTIL clk = '1'; EXIT RESET_LOOP WHEN reset = '1';

WHILE (rst = true) LOOP
x := xin;
y := yin;
WAIT UNTIL clk = '1'; EXIT RESET_LOOP WHEN reset = '1';
END LOOP;

rdy <= false;
oup <= 0;

IF (x /= 0) AND (y /= 0) THEN
WHILE (y /= 0) LOOP
WHILE (x >= y) LOOP
WAIT UNTIL clk = '1'; EXIT RESET_LOOP WHEN reset = '1';
x := x - y;
END LOOP;
h := x; x := y; y := h;
END LOOP;
END IF;

rdy <= true;
oup <= x;

END LOOP RESET_LOOP;

END PROCESS gcd;
END algorithm;
==================================================
Process Statement must contain only one Wait Statement

说是不能用两个wait
改了很多次都有错误
哪位大虾帮帮忙
把这个程序改一下
如果能运行无错

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